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<center><font size=+3><b>OPENCORES.ORG</b></font>
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<font SIZE="2">-- VHDL structural description generated from `decoder`
<p>-- date : Tue Feb 20 13:55:50 2001</p>
<p> </p>
<p>-- Entity Declaration</p>
<p>ENTITY decoder IS</p>
<p>PORT (</p>
<p>a : in BIT_VECTOR (0 TO 3); -- a</p>
<p>en : in BIT; -- en</p>
<p>ck : in BIT; -- ck</p>
<p>res : in BIT; -- res</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT; -- vss</p>
<p>c : out BIT_VECTOR (0 TO 15) -- c</p>
<p>);</p>
<p>END decoder;</p>
<p>-- Architecture Declaration</p>
<p>ARCHITECTURE VST OF decoder IS</p>
<p>COMPONENT n1_y</p>
<p>port (</p>
<p>i : in BIT; -- i</p>
<p>f : out BIT; -- f</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT a4_y</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>i2 : in BIT; -- i2</p>
<p>i3 : in BIT; -- i3</p>
<p>t : out BIT; -- t</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT a2_y</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>t : out BIT; -- t</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>SIGNAL o_0an0 : BIT; -- o_0an0</p>
<p>SIGNAL o_10an0 : BIT; -- o_10an0</p>
<p>SIGNAL o_11an0 : BIT; -- o_11an0</p>
<p>SIGNAL o_12an0 : BIT; -- o_12an0</p>
<p>SIGNAL o_13an0 : BIT; -- o_13an0</p>
<p>SIGNAL o_14an0 : BIT; -- o_14an0</p>
<p>SIGNAL o_15an0 : BIT; -- o_15an0</p>
<p>SIGNAL o_1an0 : BIT; -- o_1an0</p>
<p>SIGNAL o_2an0 : BIT; -- o_2an0</p>
<p>SIGNAL o_3an0 : BIT; -- o_3an0</p>
<p>SIGNAL o_4an0 : BIT; -- o_4an0</p>
<p>SIGNAL o_5an0 : BIT; -- o_5an0</p>
<p>SIGNAL o_6an0 : BIT; -- o_6an0</p>
<p>SIGNAL o_7an0 : BIT; -- o_7an0</p>
<p>SIGNAL o_8an0 : BIT; -- o_8an0</p>
<p>SIGNAL o_9an0 : BIT; -- o_9an0</p>
<p>SIGNAL o_inv0 : BIT; -- o_inv0</p>
<p>SIGNAL o_inv1 : BIT; -- o_inv1</p>
<p>SIGNAL o_inv2 : BIT; -- o_inv2</p>
<p>SIGNAL o_inv3 : BIT; -- o_inv3</p>
<p>BEGIN</p>
<p>inv0 : n1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>f => o_inv0,</p>
<p>i => a(0));</p>
<p>inv1 : n1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>f => o_inv1,</p>
<p>i => a(1));</p>
<p>inv2 : n1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>f => o_inv2,</p>
<p>i => a(2));</p>
<p>inv3 : n1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>f => o_inv3,</p>
<p>i => a(3));</p>
<p>noname0an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_0an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => o_inv1,</p>
<p>i1 => o_inv2,</p>
<p>i0 => o_inv3);</p>
<p>noname0an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(0),</p>
<p>i1 => o_0an0,</p>
<p>i0 => en);</p>
<p>noname1an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_1an0,</p>
<p>i3 => a(0),</p>
<p>i2 => o_inv1,</p>
<p>i1 => o_inv2,</p>
<p>i0 => o_inv3);</p>
<p>noname1an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(1),</p>
<p>i1 => o_1an0,</p>
<p>i0 => en);</p>
<p>noname2an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_2an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => a(1),</p>
<p>i1 => o_inv2,</p>
<p>i0 => o_inv3);</p>
<p>noname2an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(2),</p>
<p>i1 => o_2an0,</p>
<p>i0 => en);</p>
<p>noname3an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_3an0,</p>
<p>i3 => a(0),</p>
<p>i2 => a(1),</p>
<p>i1 => o_inv2,</p>
<p>i0 => o_inv3);</p>
<p>noname3an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(3),</p>
<p>i1 => o_3an0,</p>
<p>i0 => en);</p>
<p>noname4an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_4an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => o_inv1,</p>
<p>i1 => a(2),</p>
<p>i0 => o_inv3);</p>
<p>noname4an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(4),</p>
<p>i1 => o_4an0,</p>
<p>i0 => en);</p>
<p>noname5an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_5an0,</p>
<p>i3 => a(0),</p>
<p>i2 => o_inv1,</p>
<p>i1 => a(2),</p>
<p>i0 => o_inv3);</p>
<p>noname5an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(5),</p>
<p>i1 => o_5an0,</p>
<p>i0 => en);</p>
<p>noname6an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_6an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => a(1),</p>
<p>i1 => a(2),</p>
<p>i0 => o_inv3);</p>
<p>noname6an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(6),</p>
<p>i1 => o_6an0,</p>
<p>i0 => en);</p>
<p>noname7an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_7an0,</p>
<p>i3 => a(0),</p>
<p>i2 => a(1),</p>
<p>i1 => a(2),</p>
<p>i0 => o_inv3);</p>
<p>noname7an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(7),</p>
<p>i1 => o_7an0,</p>
<p>i0 => en);</p>
<p>noname8an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_8an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => o_inv1,</p>
<p>i1 => o_inv2,</p>
<p>i0 => a(3));</p>
<p>noname8an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(8),</p>
<p>i1 => o_8an0,</p>
<p>i0 => en);</p>
<p>noname9an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_9an0,</p>
<p>i3 => a(0),</p>
<p>i2 => o_inv1,</p>
<p>i1 => o_inv2,</p>
<p>i0 => a(3));</p>
<p>noname9an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(9),</p>
<p>i1 => o_9an0,</p>
<p>i0 => en);</p>
<p>noname10an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_10an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => a(1),</p>
<p>i1 => o_inv2,</p>
<p>i0 => a(3));</p>
<p>noname10an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(10),</p>
<p>i1 => o_10an0,</p>
<p>i0 => en);</p>
<p>noname11an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_11an0,</p>
<p>i3 => a(0),</p>
<p>i2 => a(1),</p>
<p>i1 => o_inv2,</p>
<p>i0 => a(3));</p>
<p>noname11an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(11),</p>
<p>i1 => o_11an0,</p>
<p>i0 => en);</p>
<p>noname12an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_12an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => o_inv1,</p>
<p>i1 => a(2),</p>
<p>i0 => a(3));</p>
<p>noname12an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(12),</p>
<p>i1 => o_12an0,</p>
<p>i0 => en);</p>
<p>noname13an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_13an0,</p>
<p>i3 => a(0),</p>
<p>i2 => o_inv1,</p>
<p>i1 => a(2),</p>
<p>i0 => a(3));</p>
<p>noname13an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(13),</p>
<p>i1 => o_13an0,</p>
<p>i0 => en);</p>
<p>noname14an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_14an0,</p>
<p>i3 => o_inv0,</p>
<p>i2 => a(1),</p>
<p>i1 => a(2),</p>
<p>i0 => a(3));</p>
<p>noname14an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(14),</p>
<p>i1 => o_14an0,</p>
<p>i0 => en);</p>
<p>noname15an0 : a4_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => o_15an0,</p>
<p>i3 => a(0),</p>
<p>i2 => a(1),</p>
<p>i1 => a(2),</p>
<p>i0 => a(3));</p>
<p>noname15an1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => c(15),</p>
<p>i1 => o_15an0,</p>
<p>i0 => en);</p>
<p>end VST;</p>
</font>
<b><font size=+1>Maintainers and Authors :</font></b>
<p>LCD Driver development team
<p>current members:
<ul>
<li>
<a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li>
</ul>
<p>
<b><font size=+1>Mailing-list:</font></b>
<ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul>
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<td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td>
<td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td>
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