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<center><font size=+3><b>OPENCORES.ORG</b></font>
<br><font size=-4><font color=#ffffff>.</font></font>
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<font SIZE="2">-- VHDL structural description generated from `dffres`
<p>-- date : Wed Jan 10 18:51:06 2001</p>
<p> </p>
<p>-- Entity Declaration</p>
<p>ENTITY dffres IS</p>
<p>PORT (</p>
<p>input : in BIT; -- input</p>
<p>clk : in BIT; -- clk</p>
<p>reset : in BIT; -- reset</p>
<p>output : out BIT; -- output</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END dffres;</p>
<p>-- Architecture Declaration</p>
<p>ARCHITECTURE VST OF dffres IS</p>
<p>COMPONENT inv_x1</p>
<p>port (</p>
<p>i : in BIT; -- i</p>
<p>nq : out BIT; -- nq</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT o2_x2</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>q : out BIT; -- q</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT no2_x1</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>nq : out BIT; -- nq</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT sff1_x4</p>
<p>port (</p>
<p>ck : in BIT; -- ck</p>
<p>i : in BIT; -- i</p>
<p>q : out BIT; -- q</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>SIGNAL auxsc3 : BIT; -- auxsc3</p>
<p>SIGNAL auxsc4 : BIT; -- auxsc4</p>
<p>SIGNAL auxreg1 : BIT; -- auxreg1</p>
<p>BEGIN</p>
<p>output : inv_x1</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>nq => output,</p>
<p>i => auxreg1);</p>
<p>auxsc4 : o2_x2</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>q => auxsc4,</p>
<p>i1 => auxsc3,</p>
<p>i0 => reset);</p>
<p>auxsc3 : no2_x1</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>nq => auxsc3,</p>
<p>i1 => input,</p>
<p>i0 => reset);</p>
<p>dffres_reg : sff1_x4</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>q => auxreg1,</p>
<p>i => auxsc4,</p>
<p>ck => clk);</p>
<p>end VST;</p>
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<b><font size=+1>Maintainers and Authors :</font></b>
<p>LCD Driver development team
<p>current members:
<ul>
<li>
<a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li>
</ul>
<p>
<b><font size=+1>Mailing-list:</font></b>
<ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul>
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<td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td>
<td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td>
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