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https://opencores.org/ocsvn/leros/leros/trunk
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[/] [leros/] [trunk/] [README] - Rev 3
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An FPGA optimized tiny processor core for utility functions(e.g., SW UART). The challenge is to get the resources below500 LC and use just 2 RAM blocks. The processor is named afterthe Greek island Leros where the architecture was designed.