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[/] [light8080/] [trunk/] [sw/] [tb/] [soc_tb/] [soc_tb.lst] - Rev 74
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0001 0000 ;*******************************************************************************0002 0000 ; soc_tb.asm -- light8080 SoC basic test bench.0003 0000 ;*******************************************************************************0004 0000 ; Should be used with SoC core test bench entity vhdl\test\l80soc_tb.vhdl.0005 0000 ; Assembler format compatible with TASM for DOS and Linux.0006 0000 ;*******************************************************************************0007 0000 ; This program will send a few bytes over a looped-back UART, using the UART0008 0000 ; interrupt capability and verifying that received and transmitted data match.0009 0000 ; It will then try one of the external interrupts, connected to one of the0010 0000 ; general purpose outputs.0011 0000 ; This minimal test bench relies on an already tested CPU core to do a0012 0000 ; This program does not deserve to even be called a 'test' but if if works it0013 0000 ; will at least rule out many obvious bug in the SoC core.0014 0000 ;*******************************************************************************0015 00000016 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it0017 0000 #define ds(n) \.org $+n0018 00000019 0000 MASK_RX_IRQ: .equ 20h0020 0000 MASK_TX_IRQ: .equ 10h0021 0000 MASK_RX_RDY: .equ 02h0022 0000 MASK_TX_RDY: .equ 01h0023 00000024 0000 UART_DATA: .equ 80h0025 0000 UART_STATUS: .equ 81h0026 0000 UART_BAUDL: .equ 82h0027 0000 UART_BAUDH: .equ 83h0028 0000 IRQ_ENABLE: .equ 88h0029 00000030 0000 P1IN: .equ 84h0031 0000 P2OUT: .equ 86h0032 00000033 00000034 0000 ;*******************************************************************************0035 00000036 0000 .org 0H ; Reset entry point0037 0000 C3 60 00 jmp start ; Skip the rst address area0038 00030039 0003 ;***** Interrupt vectors in area 0008h-0038h *****************0040 00030041 0008 .org 0h+(1*8) ; interrupt vector 1 (IRQ0)0042 0008 C3 12 01 jmp isr00043 0010 .org 0h+(2*8) ; interrupt vector 20044 0010 FB ei0045 0011 C9 ret0046 0018 .org 0h+(3*8) ; interrupt vector 3 (IRQ1)0047 0018 C3 1E 01 jmp isr10048 0020 .org 0h+(4*8) ; interrupt vector 40049 0020 FB ei0050 0021 C9 ret0051 0028 .org 0h+(5*8) ; interrupt vector 5 (IRQ2)0052 0028 FB ei0053 0029 C9 ret0054 0030 .org 0h+(6*8) ; interrupt vector 60055 0030 FB ei0056 0031 C9 ret0057 00320058 0038 .org 0h+(7*8) ; interrupt vector 7 (IRQ3, UART)0059 0038 C3 2A 01 int38h: jmp irq_uart ; UART interrupt0060 003B0061 003B ;***** program entry point *******************************************0062 003B0063 0060 start: .org 60H0064 0060 31 DA 01 lxi sp,stack0065 00630066 0063 ; Initialize UART RX and TX buffers0067 0063 21 74 01 lxi h,void_buffer0068 0066 22 75 01 shld ptr_tx0069 0069 21 7A 01 lxi h,rx_buffer0070 006C 22 77 01 shld ptr_rx0071 006F 3E 00 mvi a,00h0072 0071 32 79 01 sta len_rx0073 00740074 0074 ; Clear all P2 output lines (used to simulate external interrupts)0075 0074 3E 00 mvi a,00h0076 0076 D3 86 out P2OUT0077 00780078 0078 ; Set up interrupts0079 0078 3E 0B mvi a,0bh ; Enable UART irq plus IRQ0 and IRQ1...0080 007A D3 88 out IRQ_ENABLE0081 007C FB ei ; ...and enable interrupts in the CPU0082 007D0083 007D ; print hello message to console0084 007D 21 02 01 lxi h,msg_hello0085 0080 CD 66 01 call print_string0086 0083 ; Ok, now the message is being transferred through the looped back0087 0083 ; UART, using the UART interrupts, which have the lowest priority.0088 0083 ; We have plenty of time to make a few tests on the external interrupt0089 0083 ; lines before the message transmission is finished.0090 00830091 0083 ; The irq routines will leave some data at 'irq_data, each routine a0092 0083 ; different value and all non-zero. This is how we know what irq0093 0083 ; routines have executed and in which order.0094 00830095 0083 ; Test IRQ0 alone0096 0083 3E 01 mvi a,01h ; Initialize irq data0097 0085 32 73 01 sta irq_data0098 0088 3E 01 mvi a,01h ; Trigger IRQ00099 008A D3 86 out P2OUT0100 008C test_irq0:0101 008C 3A 73 01 lda irq_data0102 008F FE 04 cpi 004h ; Do we see the IRQ test data?0103 0091 CA 9C 00 jz done_irq0 ; If we do, proceed to next test0104 0094 FE 01 cpi 001h ; Do we see some other IRQ test data instead?0105 0096 C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs0106 0099 C3 8C 00 jmp test_irq0 ; Keep waiting for some IRQ test data0107 009C done_irq0:0108 009C 3E 00 mvi a,00h ; Deassert all interrupt lines0109 009E D3 86 out P2OUT0110 00A00111 00A0 ; Test IRQ1 alone0112 00A0 3E 01 mvi a,01h ; Initialize irq data0113 00A2 32 73 01 sta irq_data0114 00A5 3E 02 mvi a,02h ; Trigger IRQ10115 00A7 D3 86 out P2OUT0116 00A9 test_irq1:0117 00A9 3A 73 01 lda irq_data0118 00AC FE 02 cpi 002h ; Do we see the IRQ test data?0119 00AE CA B9 00 jz done_irq1 ; If we do, proceed to next test0120 00B1 FE 01 cpi 001h ; Do we see some other IRQ test data instead?0121 00B3 C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs0122 00B6 C3 A9 00 jmp test_irq1 ; Keep waiting for some IRQ test data0123 00B9 done_irq1:0124 00B9 AF xra a ; Deassert all interrupt lines0125 00BA D3 86 out P2OUT0126 00BC0127 00BC ; Test IRQ0 and IRQ1 simultaneously0128 00BC 3E 01 mvi a,01h ; Initialize irq data0129 00BE 32 73 01 sta irq_data0130 00C1 3E 03 mvi a,03h ; Trigger IRQ0 and IRQ10131 00C3 D3 86 out P2OUT0132 00C50133 00C5 ; Sequence IRQ0->IRQ1 will result in (1 << 2) + 1 = 50134 00C5 ; Sequence IRQ1->IRQ0 would result in (1 + 1) << 2 = 60135 00C5 ; We expect IRQ0->IRQ1, since IRQ0 has higher priority0136 00C5 test_irq01:0137 00C5 3A 73 01 lda irq_data0138 00C8 FE 05 cpi 005h ; Do we see the IRQ0->IRQ1 test data?0139 00CA CA D5 00 jz done_irq01 ; If we do, proceed to next test0140 00CD FE 01 cpi 001h ; Do we see some other IRQ test data instead?0141 00CF C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs0142 00D2 C3 C5 00 jmp test_irq01 ; Keep waiting for some IRQ test data0143 00D5 done_irq01:0144 00D5 AF xra a ; Deassert all interrupt lines0145 00D6 D3 86 out P2OUT0146 00D80147 00D8 ; Ok, the external interrupts have been tested (well, 'tested'). Now0148 00D8 ; wait for the UART looped-back transmission to end and compare0149 00D8 ; the data.0150 00D80151 00D8 ; Wait until the number of UART received characters equals the length0152 00D8 ; of the test message.0153 00D8 wait_for_message:0154 00D8 3A 79 01 lda len_rx0155 00DB FE 0F cpi msg_len0156 00DD C2 D8 00 jnz wait_for_message0157 00E00158 00E0 ; Compare the TX and RX strings0159 00E0 21 7A 01 lxi h,rx_buffer0160 00E3 11 02 01 lxi d,msg_hello0161 00E6 compare_loop:0162 00E6 1A ldax d0163 00E7 FE 24 cpi '$'0164 00E9 CA F5 00 jz test_ok0165 00EC BE cmp m0166 00ED C2 FB 00 jnz test_fail0167 00F0 23 inx h0168 00F1 13 inx d0169 00F2 C3 E6 00 jmp compare_loop0170 00F50171 00F50172 00F50173 00F50174 00F50175 00F5 test_ok:0176 00F5 3E 80 mvi a,80h ; Raise 'success' output flag...0177 00F7 D3 86 out P2OUT0178 00F9 F3 done: di ; ...and block here.0179 00FA 76 hlt0180 00FB0181 00FB test_fail:0182 00FB 3E 40 mvi a,40h ; Raise 'failure' flag...0183 00FD D3 86 out P2OUT0184 00FF C3 F9 00 jmp done ; ...and block.0185 01020186 01020187 01020188 0102 0A 0D 0A 48 msg_hello: .text "\n\r\nHello World!$"0188 0106 65 6C 6C 6F0188 010A 20 57 6F 720188 010E 6C 64 21 240189 0112 msg_end: .equ $0190 0112 msg_len: .equ msg_end - msg_hello - 10191 01120192 0112 F5 isr0: push psw0193 0113 3A 73 01 lda irq_data0194 0116 07 rlc0195 0117 07 rlc0196 0118 32 73 01 sta irq_data0197 011B F1 pop psw0198 011C FB ei0199 011D C9 ret0200 011E0201 011E F5 isr1: push psw0202 011F 3A 73 01 lda irq_data0203 0122 C6 01 adi 10204 0124 32 73 01 sta irq_data0205 0127 F1 pop psw0206 0128 FB ei0207 0129 C9 ret0208 012A0209 012A ;irq_uart: UART interrupt processing0210 012A irq_uart:0211 012A E5 push h0212 012B F5 push psw0213 012C0214 012C ; Deal with RX interrupt (if any) first and then the TX interrupt.0215 012C DB 81 in UART_STATUS ; Is there new data in the RX register?0216 012E E6 20 ani MASK_RX_IRQ0217 0130 CA 48 01 jz irq_uart_rx_done ; If there isn't, process TX interrupt.0218 01330219 0133 ; Process UART RX interrupt0220 0133 irq_uart_rx:0221 0133 3E 20 mvi a,MASK_RX_IRQ ; Clear IRQ flag.0222 0135 D3 81 out UART_STATUS0223 0137 DB 80 in UART_DATA ; Get RX byte...0224 0139 2A 77 01 lhld ptr_rx ; ...and store it in the rx buffer.0225 013C 77 mov m,a0226 013D 23 inx h0227 013E 22 77 01 shld ptr_rx ; Update the rx buffer pointer.0228 0141 3A 79 01 lda len_rx ; Update RX buffer length0229 0144 3C inr a0230 0145 32 79 01 sta len_rx0231 01480232 0148 ; Note there's no check for RX buffer overrun! we shouldn't need it0233 0148 ; here, a runaway condition would be readily apparent in the0234 0148 ; simulation, anyway.0235 01480236 0148 irq_uart_rx_done:0237 0148 ; Ok, RX is done. Now deal with TX irq, if any0238 0148 DB 81 in UART_STATUS ; Is the TX buffer re new data in the RX register?0239 014A E6 10 ani MASK_TX_IRQ0240 014C CA 62 01 jz irq_uart_end ; If there isn't, we're done.0241 014F0242 014F ; process UART TX interrupt0243 014F irq_uart_tx:0244 014F 3E 10 mvi a,MASK_TX_IRQ ; Clear IRQ flag.0245 0151 D3 81 out UART_STATUS0246 0153 2A 75 01 lhld ptr_tx ; Get next byte from the TX buffer0247 0156 7E mov a,m0248 0157 FE 24 cpi '$' ; Did we reach the end of the buffer?0249 0159 CA 62 01 jz irq_uart_tx_done ; If we did, we're done here...0250 015C 23 inx h ; ...otherwise increment the TX pointer...0251 015D 22 75 01 shld ptr_tx0252 0160 D3 80 out UART_DATA ; ...and transmit the data byte.0253 01620254 0162 irq_uart_tx_done:0255 01620256 0162 irq_uart_end:0257 0162 F1 pop psw ; Done, quit.0258 0163 E1 pop h0259 0164 FB ei0260 0165 C9 ret0261 01660262 0166 ;print_string: print $-terminated string at HL0263 0166 print_string:0264 0166 ; We don't check if there's a transmission going on0265 0166 7E mov a,m ; Get first character from string...0266 0167 23 inx h ; ...and move updated string pointer to TX0267 0168 22 75 01 shld ptr_tx ; buffer pointer.0268 016B FE 24 cpi '$' ; Kickstart transmission by sending 1st byte...0269 016D CA 72 01 jz print_string_end; ...unless its the end of string marker.0270 0170 D3 80 out UART_DATA ;0271 0172 print_string_end:0272 0172 C9 ret0273 01730274 01730275 0173 ; data space, placed immediately after object code in memory0276 0173 irq_data: ds(1)0276 01740277 0174 24 void_buffer: .text "$"0278 0175 ptr_tx: ds(2)0278 01770279 0177 ptr_rx: ds(2)0279 01790280 0179 len_rx: ds(1)0280 017A0281 017A rx_buffer: ds(32)0281 019A0282 019A ds(64)0282 01DA0283 01DA stack: ds(2)0283 01DC0284 01DC .end0285 01DC tasm: Number of errors = 0