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[/] [light8080/] [trunk/] [verilog/] [syn/] [altera_c2/] [l80soc.fit.rpt] - Rev 88
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Fitter report for l80socSun Apr 29 15:06:09 2012Quartus II 32-bit Version 11.1 Build 173 11/01/2011 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Incremental Compilation Preservation Summary6. Incremental Compilation Partition Settings7. Incremental Compilation Placement Preservation8. Pin-Out File9. Fitter Resource Usage Summary10. Fitter Partition Statistics11. Input Pins12. Output Pins13. Bidir Pins14. I/O Bank Usage15. All Package Pins16. Output Pin Default Load For Reported TCO17. Fitter Resource Utilization by Entity18. Delay Chain Summary19. Pad To Core Delay Chain Fanout20. Control Signals21. Global & Other Fast Signals22. Non-Global High Fan-Out Signals23. Fitter RAM Summary24. Interconnect Usage Summary25. LAB Logic Elements26. LAB-wide Signals27. LAB Signals Sourced28. LAB Signals Sourced Out29. LAB Distinct Inputs30. Fitter Device Options31. Operating Settings and Conditions32. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2011 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------------+; Fitter Summary ;+------------------------------------+------------------------------------------+; Fitter Status ; Successful - Sun Apr 29 15:06:08 2012 ;; Quartus II 32-bit Version ; 11.1 Build 173 11/01/2011 SJ Web Edition ;; Revision Name ; l80soc ;; Top-level Entity Name ; l80soc ;; Family ; Cyclone II ;; Device ; EP2C8Q208C8 ;; Timing Models ; Final ;; Total logic elements ; 631 / 8,256 ( 8 % ) ;; Total combinational functions ; 499 / 8,256 ( 6 % ) ;; Dedicated logic registers ; 361 / 8,256 ( 4 % ) ;; Total registers ; 361 ;; Total pins ; 24 / 138 ( 17 % ) ;; Total virtual pins ; 0 ;; Total memory bits ; 47,616 / 165,888 ( 29 % ) ;; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;; Total PLLs ; 0 / 2 ( 0 % ) ;+------------------------------------+------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; EP2C8Q208C8 ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Auto Merge PLLs ; On ; On ;; Ignore PLL Mode When Merging PLLs ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Multi-Corner Timing ; Off ; Off ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate full fit report during ECO compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; Normal ; Normal ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 2 ;; Maximum allowed ; 1 ;+----------------------------+--------++----------------------------------------------+; Incremental Compilation Preservation Summary ;+---------------------+------------------------+; Type ; Value ;+---------------------+------------------------+; Placement (by node) ; ;; -- Requested ; 0 / 927 ( 0.00 % ) ;; -- Achieved ; 0 / 927 ( 0.00 % ) ;; ; ;; Routing (by net) ; ;; -- Requested ; 0 / 0 ( 0.00 % ) ;; -- Achieved ; 0 / 0 ( 0.00 % ) ;+---------------------+------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Partition Settings ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------++------------------------------------------------------------------------------------------------------------+; Incremental Compilation Placement Preservation ;+--------------------------------+---------+-------------------+-------------------------+-------------------+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;+--------------------------------+---------+-------------------+-------------------------+-------------------+; Top ; 924 ; 0 ; N/A ; Source File ;; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ;+--------------------------------+---------+-------------------+-------------------------+-------------------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/altera_c2/l80soc.pin.+-------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+---------------------------------------------+---------------------------+; Resource ; Usage ;+---------------------------------------------+---------------------------+; Total logic elements ; 631 / 8,256 ( 8 % ) ;; -- Combinational with no register ; 270 ;; -- Register only ; 132 ;; -- Combinational with a register ; 229 ;; ; ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 331 ;; -- 3 input functions ; 73 ;; -- <=2 input functions ; 95 ;; -- Register only ; 132 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 453 ;; -- arithmetic mode ; 46 ;; ; ;; Total registers* ; 361 / 8,646 ( 4 % ) ;; -- Dedicated logic registers ; 361 / 8,256 ( 4 % ) ;; -- I/O registers ; 0 / 390 ( 0 % ) ;; ; ;; Total LABs: partially or completely used ; 51 / 516 ( 10 % ) ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 24 / 138 ( 17 % ) ;; -- Clock pins ; 2 / 4 ( 50 % ) ;; Global signals ; 2 ;; M4Ks ; 12 / 36 ( 33 % ) ;; Total block memory bits ; 47,616 / 165,888 ( 29 % ) ;; Total block memory implementation bits ; 55,296 / 165,888 ( 33 % ) ;; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;; PLLs ; 0 / 2 ( 0 % ) ;; Global clocks ; 2 / 8 ( 25 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; ASMI blocks ; 0 / 1 ( 0 % ) ;; CRC blocks ; 0 / 1 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 2% / 2% / 3% ;; Peak interconnect usage (total/H/V) ; 8% / 6% / 11% ;; Maximum fan-out node ; clock~clkctrl ;; Maximum fan-out ; 373 ;; Highest non-global fan-out signal ; reset ;; Highest non-global fan-out ; 54 ;; Total fan-out ; 3157 ;; Average fan-out ; 3.19 ;+---------------------------------------------+---------------------------+* Register count does not include registers inside RAM blocks or DSP blocks.+---------------------------------------------------------------------------------------------------+; Fitter Partition Statistics ;+---------------------------------------------+--------------------+--------------------------------+; Statistic ; Top ; hard_block:auto_generated_inst ;+---------------------------------------------+--------------------+--------------------------------+; Difficulty Clustering Region ; Low ; Low ;; ; ; ;; Total logic elements ; 631 / 8256 ( 7 % ) ; 0 / 8256 ( 0 % ) ;; -- Combinational with no register ; 270 ; 0 ;; -- Register only ; 132 ; 0 ;; -- Combinational with a register ; 229 ; 0 ;; ; ; ;; Logic element usage by number of LUT inputs ; ; ;; -- 4 input functions ; 331 ; 0 ;; -- 3 input functions ; 73 ; 0 ;; -- <=2 input functions ; 95 ; 0 ;; -- Register only ; 132 ; 0 ;; ; ; ;; Logic elements by mode ; ; ;; -- normal mode ; 453 ; 0 ;; -- arithmetic mode ; 46 ; 0 ;; ; ; ;; Total registers ; 361 ; 0 ;; -- Dedicated logic registers ; 361 / 8256 ( 4 % ) ; 0 / 8256 ( 0 % ) ;; -- I/O registers ; 0 ; 0 ;; ; ; ;; Total LABs: partially or completely used ; 51 / 516 ( 9 % ) ; 0 / 516 ( 0 % ) ;; ; ; ;; Virtual pins ; 0 ; 0 ;; I/O pins ; 24 ; 0 ;; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ; 0 / 36 ( 0 % ) ;; Total memory bits ; 47616 ; 0 ;; Total RAM block bits ; 55296 ; 0 ;; M4K ; 12 / 36 ( 33 % ) ; 0 / 36 ( 0 % ) ;; Clock control block ; 2 / 10 ( 20 % ) ; 0 / 10 ( 0 % ) ;; ; ; ;; Connections ; ; ;; -- Input Connections ; 0 ; 0 ;; -- Registered Input Connections ; 0 ; 0 ;; -- Output Connections ; 0 ; 0 ;; -- Registered Output Connections ; 0 ; 0 ;; ; ; ;; Internal Connections ; ; ;; -- Total Connections ; 3196 ; 0 ;; -- Registered Connections ; 978 ; 0 ;; ; ; ;; External Connections ; ; ;; -- Top ; 0 ; 0 ;; -- hard_block:auto_generated_inst ; 0 ; 0 ;; ; ; ;; Partition Interface ; ; ;; -- Input Ports ; 7 ; 0 ;; -- Output Ports ; 1 ; 0 ;; -- Bidir Ports ; 16 ; 0 ;; ; ; ;; Registered Ports ; ; ;; -- Registered Input Ports ; 0 ; 0 ;; -- Registered Output Ports ; 0 ; 0 ;; ; ; ;; Port Connectivity ; ; ;; -- Input Ports driven by GND ; 0 ; 0 ;; -- Output Ports driven by GND ; 0 ; 0 ;; -- Input Ports driven by VCC ; 0 ; 0 ;; -- Output Ports driven by VCC ; 0 ; 0 ;; -- Input Ports with no Source ; 0 ; 0 ;; -- Output Ports with no Source ; 0 ; 0 ;; -- Input Ports with no Fanout ; 0 ; 0 ;; -- Output Ports with no Fanout ; 0 ; 0 ;+---------------------------------------------+--------------------+--------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; clock ; 23 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; extint[0] ; 176 ; 2 ; 23 ; 19 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; extint[1] ; 27 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; extint[2] ; 127 ; 3 ; 34 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; extint[3] ; 28 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; reset ; 24 ; 1 ; 0 ; 9 ; 1 ; 55 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; rxd ; 94 ; 4 ; 28 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; txd ; 99 ; 4 ; 30 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Bidir Pins ;+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; p1dio[0] ; 77 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[0] ; - ;; p1dio[1] ; 90 ; 4 ; 28 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[1] ; - ;; p1dio[2] ; 118 ; 3 ; 34 ; 7 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[2] ; - ;; p1dio[3] ; 81 ; 4 ; 23 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[3] ; - ;; p1dio[4] ; 76 ; 4 ; 18 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[4] ; - ;; p1dio[5] ; 80 ; 4 ; 23 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[5] ; - ;; p1dio[6] ; 89 ; 4 ; 28 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[6] ; - ;; p1dio[7] ; 92 ; 4 ; 28 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p1dir[7] ; - ;; p2dio[0] ; 82 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[0] ; - ;; p2dio[1] ; 87 ; 4 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[1] ; - ;; p2dio[2] ; 128 ; 3 ; 34 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[2] ; - ;; p2dio[3] ; 116 ; 3 ; 34 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[3] ; - ;; p2dio[4] ; 88 ; 4 ; 25 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[4] ; - ;; p2dio[5] ; 173 ; 2 ; 25 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[5] ; - ;; p2dio[6] ; 84 ; 4 ; 25 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[6] ; - ;; p2dio[7] ; 86 ; 4 ; 25 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; p2dir[7] ; - ;+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 6 / 32 ( 19 % ) ; 3.3V ; -- ;; 2 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ;; 3 ; 5 / 35 ( 14 % ) ; 3.3V ; -- ;; 4 ; 14 / 36 ( 39 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 5 ; 4 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 6 ; 5 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 8 ; 6 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 10 ; 7 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 11 ; 8 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 12 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 13 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 14 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 15 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 16 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; 17 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; 18 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; 19 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; 20 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;; 21 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;; 22 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; 23 ; 27 ; 1 ; clock ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 24 ; 28 ; 1 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 26 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; 27 ; 30 ; 1 ; extint[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 28 ; 31 ; 1 ; extint[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 30 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 31 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 32 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 33 ; 35 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 34 ; 36 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 35 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 36 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 37 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 38 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 39 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 40 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 41 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 42 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 43 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 44 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 45 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 46 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 47 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 48 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 50 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; 51 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 52 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; 53 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 54 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; 55 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 56 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 57 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 58 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 59 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 60 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 61 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 62 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 63 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 64 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 66 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 67 ; 69 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 68 ; 70 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 69 ; 71 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 70 ; 74 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 71 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 72 ; 75 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 73 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 74 ; 76 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 75 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 76 ; 78 ; 4 ; p1dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 77 ; 79 ; 4 ; p1dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 79 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 80 ; 82 ; 4 ; p1dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 81 ; 83 ; 4 ; p1dio[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 82 ; 84 ; 4 ; p2dio[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 83 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 84 ; 85 ; 4 ; p2dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 85 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 86 ; 86 ; 4 ; p2dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 87 ; 87 ; 4 ; p2dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 88 ; 88 ; 4 ; p2dio[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 89 ; 89 ; 4 ; p1dio[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 90 ; 90 ; 4 ; p1dio[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 91 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 92 ; 91 ; 4 ; p1dio[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 94 ; 92 ; 4 ; rxd ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 95 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 96 ; 94 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 97 ; 95 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 98 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 99 ; 96 ; 4 ; txd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 100 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 101 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 102 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 103 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 104 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 105 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 106 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 107 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 108 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 109 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 110 ; 107 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 112 ; 108 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 113 ; 109 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 114 ; 110 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 115 ; 112 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 116 ; 113 ; 3 ; p2dio[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 117 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 118 ; 117 ; 3 ; p1dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 119 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 120 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 121 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; 122 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 123 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; 124 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 125 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; 126 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; 127 ; 125 ; 3 ; extint[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 128 ; 126 ; 3 ; p2dio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 129 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 130 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 131 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 132 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 133 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 134 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 135 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 136 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 137 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 138 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 139 ; 136 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 141 ; 137 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 142 ; 138 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 143 ; 141 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 144 ; 142 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 145 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 146 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 147 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 148 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 149 ; 151 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 150 ; 152 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 151 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 152 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 153 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 154 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; 155 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 156 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; 157 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 158 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; 159 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 160 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 161 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 162 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 163 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 164 ; 159 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 165 ; 160 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 166 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 167 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 168 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 169 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 170 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 171 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 172 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 173 ; 165 ; 2 ; p2dio[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 174 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 175 ; 168 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 176 ; 169 ; 2 ; extint[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 177 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 178 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 179 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 180 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 181 ; 175 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 182 ; 176 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 183 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 184 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 185 ; 180 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 186 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 187 ; 181 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 188 ; 182 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 189 ; 183 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 190 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 191 ; 184 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 192 ; 185 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 193 ; 186 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 194 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 195 ; 187 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 196 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 197 ; 191 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 198 ; 192 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 199 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 200 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 201 ; 197 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 202 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 203 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 204 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 205 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 206 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 207 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 208 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------------+-------+------------------------------------+; 3.3-V LVTTL ; 0 pF ; Not Available ;; 3.3-V LVCMOS ; 0 pF ; Not Available ;; 2.5 V ; 0 pF ; Not Available ;; 1.8 V ; 0 pF ; Not Available ;; 1.5 V ; 0 pF ; Not Available ;; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;; LVDS ; 0 pF ; 100 Ohm (Differential) ;; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;; RSDS ; 0 pF ; 100 Ohm (Differential) ;; Simple RSDS ; 0 pF ; Not Available ;; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;+----------------------------------+-------+------------------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+; |l80soc ; 631 (103) ; 361 (62) ; 0 (0) ; 47616 ; 12 ; 0 ; 0 ; 0 ; 24 ; 0 ; 270 (37) ; 132 (36) ; 229 (18) ; |l80soc ; ;; |intr_ctrl:intrc| ; 25 (25) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 1 (1) ; 17 (17) ; |l80soc|intr_ctrl:intrc ; ;; |light8080:cpu| ; 429 (429) ; 222 (222) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 207 (207) ; 77 (77) ; 145 (145) ; |l80soc|light8080:cpu ; ;; |micro_rom:rom| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom ; ;; |altsyncram:Ram0_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0 ; ;; |altsyncram_ts61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 14848 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated ; ;; |ram_image:ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram ; ;; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_0 ; ;; |altsyncram_tv81:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |l80soc|ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated ; ;; |uart:uart| ; 90 (90) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 18 (18) ; 53 (53) ; |l80soc|uart:uart ; ;+----------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+------------------------------------------------------------------------------------+; Delay Chain Summary ;+-----------+----------+---------------+---------------+-----------------------+-----+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;+-----------+----------+---------------+---------------+-----------------------+-----+; p1dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p1dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p1dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;; p1dio[3] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p1dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p1dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p1dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p1dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p2dio[0] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p2dio[1] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p2dio[2] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;; p2dio[3] ; Bidir ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;; p2dio[4] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p2dio[5] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p2dio[6] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; p2dio[7] ; Bidir ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; txd ; Output ; -- ; -- ; -- ; -- ;; clock ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;; reset ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;; extint[1] ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;; extint[3] ; Input ; (0) 351 ps ; (0) 351 ps ; -- ; -- ;; extint[2] ; Input ; (6) 4641 ps ; (6) 4641 ps ; -- ; -- ;; extint[0] ; Input ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;; rxd ; Input ; (6) 4686 ps ; (6) 4686 ps ; -- ; -- ;+-----------+----------+---------------+---------------+-----------------------+-----++----------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+----------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+----------------------------------+-------------------+---------+; p1dio[0] ; ; ;; - io_dout~3 ; 0 ; 6 ;; p1dio[1] ; ; ;; - io_dout~7 ; 0 ; 6 ;; p1dio[2] ; ; ;; - io_dout~9 ; 0 ; 6 ;; p1dio[3] ; ; ;; - io_dout~11 ; 0 ; 6 ;; p1dio[4] ; ; ;; - io_dout~14 ; 1 ; 6 ;; p1dio[5] ; ; ;; - io_dout~15 ; 0 ; 6 ;; p1dio[6] ; ; ;; - io_dout~17 ; 1 ; 6 ;; p1dio[7] ; ; ;; - io_dout~19 ; 0 ; 6 ;; p2dio[0] ; ; ;; - io_dout~2 ; 0 ; 6 ;; p2dio[1] ; ; ;; - io_dout~7 ; 0 ; 6 ;; p2dio[2] ; ; ;; - io_dout~9 ; 0 ; 6 ;; p2dio[3] ; ; ;; - io_dout~11 ; 1 ; 6 ;; p2dio[4] ; ; ;; - io_dout~13 ; 1 ; 6 ;; p2dio[5] ; ; ;; - io_dout~15 ; 0 ; 6 ;; p2dio[6] ; ; ;; - io_dout~17 ; 1 ; 6 ;; p2dio[7] ; ; ;; - io_dout~19 ; 1 ; 6 ;; clock ; ; ;; reset ; ; ;; extint[1] ; ; ;; extint[3] ; ; ;; extint[2] ; ; ;; - intr_ctrl:intrc|act_int~4 ; 1 ; 6 ;; extint[0] ; ; ;; - intr_ctrl:intrc|act_int~6 ; 0 ; 6 ;; rxd ; ; ;; - uart:uart|sserIn~feeder ; 0 ; 6 ;+----------------------------------+-------------------+---------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+; clock ; PIN_23 ; 373 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;; comb~0 ; LCCOMB_X23_Y12_N26 ; 8 ; Write enable ; no ; -- ; -- ; -- ;; intr_ctrl:intrc|Selector2~2 ; LCCOMB_X21_Y10_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; intr_ctrl:intrc|cpu_inst[5]~7 ; LCCOMB_X23_Y10_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; intr_ena[0]~1 ; LCCOMB_X23_Y8_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; io_dout[4]~5 ; LCCOMB_X24_Y7_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|Equal18~0 ; LCCOMB_X26_Y10_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ;; light8080:cpu|T1[4]~3 ; LCCOMB_X24_Y12_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|T2[4]~3 ; LCCOMB_X23_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|addr_low[3]~1 ; LCCOMB_X28_Y10_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|flag_reg[6]~10 ; LCCOMB_X26_Y10_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~209 ; LCCOMB_X25_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~211 ; LCCOMB_X25_Y14_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~213 ; LCCOMB_X25_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~215 ; LCCOMB_X25_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~217 ; LCCOMB_X25_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~219 ; LCCOMB_X24_Y13_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~221 ; LCCOMB_X24_Y13_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~223 ; LCCOMB_X26_Y14_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~225 ; LCCOMB_X26_Y12_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~227 ; LCCOMB_X25_Y10_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~229 ; LCCOMB_X25_Y13_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~231 ; LCCOMB_X26_Y12_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~233 ; LCCOMB_X25_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~235 ; LCCOMB_X25_Y12_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~237 ; LCCOMB_X25_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|rbank~239 ; LCCOMB_X26_Y14_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|uc_decode~0 ; LCCOMB_X28_Y13_N18 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|uc_ret_addr[6]~1 ; LCCOMB_X28_Y15_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; light8080:cpu|ucode_field2[7] ; LCFF_X28_Y10_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; p1dir[0] ; LCFF_X26_Y7_N15 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[0]~0 ; LCCOMB_X26_Y7_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; p1dir[1] ; LCFF_X26_Y7_N21 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[2] ; LCFF_X26_Y7_N3 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[3] ; LCFF_X26_Y7_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[4] ; LCFF_X26_Y7_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[5] ; LCFF_X26_Y7_N29 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[6] ; LCFF_X26_Y7_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1dir[7] ; LCFF_X26_Y7_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p1reg[0]~0 ; LCCOMB_X23_Y7_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; p2dir[0] ; LCFF_X26_Y8_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[0]~0 ; LCCOMB_X26_Y8_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; p2dir[1] ; LCFF_X26_Y8_N23 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[2] ; LCFF_X26_Y8_N25 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[3] ; LCFF_X26_Y8_N31 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[4] ; LCFF_X26_Y8_N9 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[5] ; LCFF_X26_Y8_N11 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[6] ; LCFF_X26_Y8_N13 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2dir[7] ; LCFF_X26_Y8_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ;; p2reg[0]~0 ; LCCOMB_X25_Y7_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; reset ; PIN_24 ; 55 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;; reset ; PIN_24 ; 138 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;; uart:uart|Equal5~10 ; LCCOMB_X25_Y8_N28 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;; uart:uart|rxBaudCnt[0]~1 ; LCCOMB_X21_Y8_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; uart:uart|rxBitCnt[1]~12 ; LCCOMB_X22_Y8_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; uart:uart|rxBusy ; LCFF_X21_Y8_N13 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ;; uart:uart|rxData[0]~0 ; LCCOMB_X21_Y8_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; uart:uart|rxShiftReg[0]~0 ; LCCOMB_X21_Y8_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; uart:uart|txBitCnt[3]~6 ; LCCOMB_X28_Y8_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; uart:uart|txBusy ; LCFF_X28_Y8_N17 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;; uart:uart|txShiftReg[1]~4 ; LCCOMB_X28_Y9_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;; uart:uart|txShiftReg~2 ; LCCOMB_X28_Y9_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; uartbaud[15]~3 ; LCCOMB_X23_Y8_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; uartbaud[7]~2 ; LCCOMB_X25_Y8_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;+--------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------++--------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+-------+----------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-------+----------+---------+----------------------+------------------+---------------------------+; clock ; PIN_23 ; 373 ; Global Clock ; GCLK2 ; -- ;; reset ; PIN_24 ; 138 ; Global Clock ; GCLK1 ; -- ;+-------+----------+---------+----------------------+------------------+---------------------------++----------------------------------------------------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+------------------------------------------------------------------------------------------------+---------+; Name ; Fan-Out ;+------------------------------------------------------------------------------------------------+---------+; reset ; 54 ;; light8080:cpu|inta_reg ; 42 ;; light8080:cpu|Mux10~1 ; 31 ;; light8080:cpu|Mux11~1 ; 31 ;; light8080:cpu|Mux8~1 ; 31 ;; light8080:cpu|Mux9~1 ; 31 ;; light8080:cpu|uc_decode~0 ; 28 ;; uart:uart|txBusy ; 24 ;; light8080:cpu|ucode_field2[4] ; 22 ;; light8080:cpu|ucode_field2[1] ; 21 ;; light8080:cpu|Mux27~1 ; 20 ;; light8080:cpu|DO[4]~1 ; 20 ;; light8080:cpu|Mux24~8 ; 19 ;; light8080:cpu|Mux22~3 ; 19 ;; light8080:cpu|Mux21~3 ; 19 ;; light8080:cpu|ucode_field2[2] ; 19 ;; light8080:cpu|ucode_field2[0] ; 19 ;; light8080:cpu|DO[2]~0 ; 19 ;; light8080:cpu|Mux26~5 ; 18 ;; light8080:cpu|ucode_field2[18] ; 18 ;; light8080:cpu|ucode_field2[17] ; 18 ;; light8080:cpu|ucode_field2[16] ; 18 ;; light8080:cpu|ucode_field2[6] ; 17 ;; light8080:cpu|ucode_field2[15] ; 17 ;; light8080:cpu|Mux20~3 ; 17 ;; light8080:cpu|uc_end~1 ; 17 ;; light8080:cpu|Mux0~5 ; 17 ;; uart:uart|Equal5~10 ; 17 ;; light8080:cpu|we_rb~0 ; 16 ;; light8080:cpu|ucode_field2[3] ; 16 ;; light8080:cpu|addr_low[1] ; 16 ;; light8080:cpu|addr_low[3] ; 15 ;; light8080:cpu|addr_low[2] ; 15 ;; light8080:cpu|addr_low[0] ; 15 ;; light8080:cpu|Equal13~0 ; 13 ;; uart:uart|rxBusy ; 12 ;; uart:uart|baudCE16 ; 12 ;; light8080:cpu|rbank~207 ; 11 ;; light8080:cpu|rbank~197 ; 11 ;; light8080:cpu|rbank~187 ; 11 ;; light8080:cpu|rbank~177 ; 11 ;; light8080:cpu|Mux0~4 ; 11 ;; light8080:cpu|uc_do_ret~0 ; 11 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a26 ; 11 ;; light8080:cpu|Equal19~1 ; 10 ;; io_dout[4]~0 ; 9 ;; light8080:cpu|T1[0] ; 9 ;; light8080:cpu|DO[3] ; 9 ;; light8080:cpu|DO[1] ; 9 ;; light8080:cpu|DO[0] ; 9 ;; light8080:cpu|addr_low[4] ; 9 ;; light8080:cpu|addr_low[5] ; 9 ;; light8080:cpu|addr_low[6] ; 9 ;; light8080:cpu|addr_low[7] ; 9 ;; light8080:cpu|DO[2] ; 9 ;; uart:uart|rxShiftReg[0]~0 ; 8 ;; uart:uart|rxData[0]~0 ; 8 ;; light8080:cpu|T2[4]~3 ; 8 ;; light8080:cpu|T2~1 ; 8 ;; light8080:cpu|T2~0 ; 8 ;; light8080:cpu|T1[4]~3 ; 8 ;; light8080:cpu|T1~1 ; 8 ;; light8080:cpu|T1~0 ; 8 ;; light8080:cpu|rbank~239 ; 8 ;; light8080:cpu|rbank~237 ; 8 ;; light8080:cpu|rbank~235 ; 8 ;; light8080:cpu|rbank~233 ; 8 ;; light8080:cpu|rbank~231 ; 8 ;; light8080:cpu|rbank~229 ; 8 ;; light8080:cpu|rbank~227 ; 8 ;; light8080:cpu|rbank~225 ; 8 ;; light8080:cpu|rbank~223 ; 8 ;; light8080:cpu|rbank~221 ; 8 ;; light8080:cpu|rbank~219 ; 8 ;; light8080:cpu|rbank~217 ; 8 ;; light8080:cpu|rbank~215 ; 8 ;; light8080:cpu|rbank~213 ; 8 ;; light8080:cpu|rbank~211 ; 8 ;; light8080:cpu|rbank~209 ; 8 ;; light8080:cpu|T1[2] ; 8 ;; light8080:cpu|uc_ret_addr[6]~1 ; 8 ;; comb~0 ; 8 ;; io_dout[4]~5 ; 8 ;; light8080:cpu|ucode_field2[7] ; 8 ;; light8080:cpu|ucode_field2[5] ; 8 ;; p2dir[0]~0 ; 8 ;; p2reg[0]~0 ; 8 ;; p1dir[0]~0 ; 8 ;; p1reg[0]~0 ; 8 ;; Equal2~2 ; 8 ;; uartbaud[15]~3 ; 8 ;; light8080:cpu|DO[7] ; 8 ;; light8080:cpu|DO[6] ; 8 ;; light8080:cpu|DO[5] ; 8 ;; uartbaud[7]~2 ; 8 ;; light8080:cpu|addr_low[3]~1 ; 8 ;; scpu_io ; 8 ;; always0~0 ; 8 ;; light8080:cpu|DO[4] ; 8 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a20 ; 8 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a27 ; 8 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a28 ; 8 ;; light8080:cpu|T1[3] ; 7 ;; io_dout~6 ; 7 ;; intr_ctrl:intrc|intSq.10 ; 7 ;; light8080:cpu|T1[1] ; 7 ;; light8080:cpu|do_reset ; 7 ;; intr_ctrl:intrc|cpu_inst[0] ; 7 ;; uart:uart|txShiftReg[1]~4 ; 7 ;; intr_ena[0]~0 ; 7 ;; light8080:cpu|flag_reg[0] ; 7 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a29 ; 7 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a30 ; 7 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a31 ; 7 ;; intr_ctrl:intrc|cpu_inst[5]~6 ; 6 ;; intr_ctrl:intrc|Selector2~2 ; 6 ;; light8080:cpu|Mux25~1 ; 6 ;; light8080:cpu|T1[7] ; 6 ;; intr_ctrl:intrc|act_int[0] ; 5 ;; uart:uart|rxBaudCnt[0] ; 5 ;; light8080:cpu|Mux25~0 ; 5 ;; light8080:cpu|T1[4] ; 5 ;; light8080:cpu|T1[5] ; 5 ;; light8080:cpu|T1[6] ; 5 ;; light8080:cpu|IR[5] ; 5 ;; light8080:cpu|Mux5~8 ; 5 ;; cpu_din[2]~5 ; 5 ;; Equal7~1 ; 5 ;; uart:uart|Equal0~0 ; 5 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a19 ; 5 ;; light8080:cpu|Mux0~8 ; 4 ;; light8080:cpu|Mux1~6 ; 4 ;; light8080:cpu|Mux2~6 ; 4 ;; light8080:cpu|Mux3~6 ; 4 ;; light8080:cpu|Mux4~6 ; 4 ;; light8080:cpu|Mux6~6 ; 4 ;; light8080:cpu|Mux7~6 ; 4 ;; intr_ena[0]~1 ; 4 ;; uart:uart|rxBitCnt[1]~12 ; 4 ;; uart:uart|rxBaudCnt[0]~1 ; 4 ;; intr_ctrl:intrc|act_int[2] ; 4 ;; uart:uart|rxBaudCnt[1] ; 4 ;; uart:uart|rxBaudCnt[3] ; 4 ;; light8080:cpu|load_psw~1 ; 4 ;; light8080:cpu|ucode_field2[14] ; 4 ;; light8080:cpu|Mux20~2 ; 4 ;; light8080:cpu|Mux20~0 ; 4 ;; intr_ctrl:intrc|cpu_inst[0]~2 ; 4 ;; intr_ctrl:intrc|intSq.00 ; 4 ;; io_dout[4]~1 ; 4 ;; light8080:cpu|Equal18~0 ; 4 ;; light8080:cpu|Equal19~0 ; 4 ;; uart:uart|txBitCnt[3]~6 ; 4 ;; light8080:cpu|IR[4] ; 4 ;; cpu_din[5]~11 ; 4 ;; cpu_din[4]~9 ; 4 ;; cpu_din[3]~7 ; 4 ;; cpu_din[1]~3 ; 4 ;; light8080:cpu|uc_end~0 ; 4 ;; light8080:cpu|uc_do_jmp~0 ; 4 ;; cpu_din[0]~1 ; 4 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a21 ; 4 ;; light8080:cpu|inte_reg ; 4 ;; uartbaud[7]~4 ; 3 ;; uart:uart|sserIn ; 3 ;; uart:uart|Equal3~1 ; 3 ;; light8080:cpu|flag_reg[6]~10 ; 3 ;; intr_ctrl:intrc|Equal0~0 ; 3 ;; intr_ctrl:intrc|act_int[3] ; 3 ;; intr_ctrl:intrc|act_int[1] ; 3 ;; uart:uart|Equal4~0 ; 3 ;; uart:uart|Equal3~0 ; 3 ;; uart:uart|rxBaudCnt[2] ; 3 ;; light8080:cpu|ucode_field2[22] ; 3 ;; light8080:cpu|ucode_field2[21] ; 3 ;; light8080:cpu|ucode_field2[24] ; 3 ;; light8080:cpu|Mux25~2 ; 3 ;; light8080:cpu|T2[4] ; 3 ;; light8080:cpu|daa_test2~0 ; 3 ;; intr_ctrl:intrc|intSq.01 ; 3 ;; intr_ctrl:intrc|intSel.00 ; 3 ;; light8080:cpu|flag_reg[7] ; 3 ;; light8080:cpu|cy_in~0 ; 3 ;; always1~0 ; 3 ;; light8080:cpu|rbank~167 ; 3 ;; light8080:cpu|rbank~157 ; 3 ;; light8080:cpu|rbank~147 ; 3 ;; light8080:cpu|rbank~137 ; 3 ;; light8080:cpu|IR[3] ; 3 ;; cpu_din[7]~15 ; 3 ;; cpu_din[6]~13 ; 3 ;; Equal7~0 ; 3 ;; uart:uart|txShiftReg~0 ; 3 ;; light8080:cpu|daa_res9[5] ; 3 ;; light8080:cpu|int_pending ; 3 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a4 ; 3 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a5 ; 3 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a3 ; 3 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a2 ; 3 ;; intr_ctrl:intrc|cpu_inst[5]~7 ; 2 ;; light8080:cpu|uc_di~0 ; 2 ;; light8080:cpu|daa_test1~0 ; 2 ;; uart:uart|rxShiftReg[7] ; 2 ;; uart:uart|rxShiftReg[6] ; 2 ;; uart:uart|rxShiftReg[5] ; 2 ;; uart:uart|rxShiftReg[4] ; 2 ;; uart:uart|rxValid ; 2 ;; uart:uart|rxShiftReg[3] ; 2 ;; uart:uart|rxShiftReg[2] ; 2 ;; uart:uart|rxShiftReg[1] ; 2 ;; light8080:cpu|ucode_field2[9] ; 2 ;; light8080:cpu|always8~0 ; 2 ;; light8080:cpu|ucode_field2[8] ; 2 ;; light8080:cpu|Mux24~5 ; 2 ;; light8080:cpu|Mux26~3 ; 2 ;; light8080:cpu|Mux26~0 ; 2 ;; light8080:cpu|Mux25~7 ; 2 ;; light8080:cpu|Mux25~6 ; 2 ;; light8080:cpu|Mux25~3 ; 2 ;; light8080:cpu|Mux20~4 ; 2 ;; light8080:cpu|T2[1] ; 2 ;; light8080:cpu|T2[2] ; 2 ;; light8080:cpu|T2[3] ; 2 ;; light8080:cpu|arith_op2_sgn[4]~4 ; 2 ;; light8080:cpu|T2[5] ; 2 ;; light8080:cpu|T2[6] ; 2 ;; light8080:cpu|daa_test2~1 ; 2 ;; light8080:cpu|T2[7] ; 2 ;; intr_ctrl:intrc|intSel.01 ; 2 ;; intr_ctrl:intrc|intSel.10 ; 2 ;; rxfull ; 2 ;; light8080:cpu|Mux28~0 ; 2 ;; intr_ctrl:intrc|cpu_inst[5]~4 ; 2 ;; light8080:cpu|ucode_field2[19] ; 2 ;; light8080:cpu|T2[0] ; 2 ;; Equal2~1 ; 2 ;; Equal2~0 ; 2 ;; light8080:cpu|Mux0~7 ; 2 ;; light8080:cpu|Mux1~5 ; 2 ;; light8080:cpu|Mux2~5 ; 2 ;; light8080:cpu|Mux3~5 ; 2 ;; light8080:cpu|Mux4~5 ; 2 ;; light8080:cpu|Mux5~6 ; 2 ;; light8080:cpu|Mux6~5 ; 2 ;; light8080:cpu|Mux7~5 ; 2 ;; uart:uart|txShiftReg~2 ; 2 ;; uart:uart|serOut ; 2 ;; light8080:cpu|delayed_ei ; 2 ;; uart:uart|rxBitCnt[2] ; 2 ;; uart:uart|rxBitCnt[1] ; 2 ;; uart:uart|rxBitCnt[0] ; 2 ;; uart:uart|rxBitCnt[3] ; 2 ;; light8080:cpu|Add1~18 ; 2 ;; light8080:cpu|flag_reg[4] ; 2 ;; light8080:cpu|daa_res9[1] ; 2 ;; light8080:cpu|daa_res9[6] ; 2 ;; light8080:cpu|flag_reg[6] ; 2 ;; light8080:cpu|flag_reg[2] ; 2 ;; light8080:cpu|addr_plus_1[7]~14 ; 2 ;; light8080:cpu|addr_plus_1[6]~12 ; 2 ;; light8080:cpu|addr_plus_1[5]~10 ; 2 ;; light8080:cpu|addr_plus_1[4]~8 ; 2 ;; light8080:cpu|addr_plus_1[3]~6 ; 2 ;; light8080:cpu|addr_plus_1[2]~4 ; 2 ;; light8080:cpu|addr_plus_1[1]~2 ; 2 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a1 ; 2 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a0 ; 2 ;; light8080:cpu|addr_plus_1[0]~0 ; 2 ;; light8080:cpu|condition_reg ; 2 ;; uart:uart|txBitCnt[3] ; 2 ;; uart:uart|txBitCnt[1] ; 2 ;; uart:uart|txBitCnt[2] ; 2 ;; uart:uart|txBitCnt[0] ; 2 ;; uart:uart|baudCount[14] ; 2 ;; uart:uart|baudCount[15] ; 2 ;; uart:uart|baudCount[12] ; 2 ;; uart:uart|baudCount[13] ; 2 ;; uart:uart|baudCount[10] ; 2 ;; uart:uart|baudCount[11] ; 2 ;; uart:uart|baudCount[8] ; 2 ;; uart:uart|baudCount[9] ; 2 ;; uart:uart|baudCount[6] ; 2 ;; uart:uart|baudCount[7] ; 2 ;; uart:uart|baudCount[4] ; 2 ;; uart:uart|baudCount[5] ; 2 ;; uart:uart|baudCount[2] ; 2 ;; uart:uart|baudCount[3] ; 2 ;; uart:uart|baudCount[0] ; 2 ;; uart:uart|baudCount[1] ; 2 ;; uart:uart|txBaudCnt[3] ; 2 ;; uart:uart|txBaudCnt[2] ; 2 ;; uart:uart|txBaudCnt[1] ; 2 ;; uart:uart|txBaudCnt[0] ; 2 ;; rxd ; 1 ;; extint[0] ; 1 ;; extint[2] ; 1 ;; extint[3] ; 1 ;; extint[1] ; 1 ;; p2dio[7]~7 ; 1 ;; p2dio[6]~6 ; 1 ;; p2dio[5]~5 ; 1 ;; p2dio[4]~4 ; 1 ;; p2dio[3]~3 ; 1 ;; p2dio[2]~2 ; 1 ;; p2dio[1]~1 ; 1 ;; p2dio[0]~0 ; 1 ;; p1dio[7]~7 ; 1 ;; p1dio[6]~6 ; 1 ;; p1dio[5]~5 ; 1 ;; p1dio[4]~4 ; 1 ;; p1dio[3]~3 ; 1 ;; p1dio[2]~2 ; 1 ;; p1dio[1]~1 ; 1 ;; p1dio[0]~0 ; 1 ;; uart:uart|rxBaudCnt[0]~4 ; 1 ;; intr_ctrl:intrc|intSel.00~0 ; 1 ;; light8080:cpu|DO[4]~13 ; 1 ;; light8080:cpu|flag_reg~18 ; 1 ;; intr_ctrl:intrc|Selector2~3 ; 1 ;; intr_ctrl:intrc|Selector0~2 ; 1 ;; light8080:cpu|data_output[6]~13 ; 1 ;; light8080:cpu|data_output[5]~12 ; 1 ;; light8080:cpu|data_output[3]~11 ; 1 ;; light8080:cpu|Mux24~9 ; 1 ;; light8080:cpu|DO[4]~12 ; 1 ;; light8080:cpu|data_output[0]~10 ; 1 ;; light8080:cpu|Mux5~10 ; 1 ;; light8080:cpu|Mux5~9 ; 1 ;; uart:uart|txShiftReg~11 ; 1 ;; uart:uart|txShiftReg~10 ; 1 ;; uart:uart|txShiftReg[8] ; 1 ;; uart:uart|txShiftReg~9 ; 1 ;; uart:uart|txShiftReg[7] ; 1 ;; light8080:cpu|delayed_ei~1 ; 1 ;; light8080:cpu|delayed_ei~0 ; 1 ;; uart:uart|txShiftReg~8 ; 1 ;; uart:uart|txShiftReg[6] ; 1 ;; uart:uart|rxValid~0 ; 1 ;; uart:uart|rxShiftReg[0]~1 ; 1 ;; intr_ctrl:intrc|act_int~7 ; 1 ;; intr_ctrl:intrc|act_int~6 ; 1 ;; intr_ena[0] ; 1 ;; intr_ctrl:intrc|act_int~5 ; 1 ;; intr_ctrl:intrc|act_int~4 ; 1 ;; intr_ena[2] ; 1 ;; intr_ctrl:intrc|act_int~3 ; 1 ;; intr_ctrl:intrc|intSel.11 ; 1 ;; intr_ctrl:intrc|act_int~2 ; 1 ;; intr_ena[3] ; 1 ;; intr_ctrl:intrc|act_int~1 ; 1 ;; intr_ctrl:intrc|act_int~0 ; 1 ;; intr_ena[1] ; 1 ;; light8080:cpu|inte_reg~0 ; 1 ;; uart:uart|rxBaudCnt[1]~3 ; 1 ;; uart:uart|rxBaudCnt[2]~2 ; 1 ;; uart:uart|rxBaudCnt~0 ; 1 ;; uart:uart|rxBusy~1 ; 1 ;; uart:uart|rxBusy~0 ; 1 ;; light8080:cpu|Equal2~1 ; 1 ;; light8080:cpu|Equal13~2 ; 1 ;; light8080:cpu|Equal11~0 ; 1 ;; uart:uart|txShiftReg~7 ; 1 ;; uart:uart|txShiftReg[5] ; 1 ;; light8080:cpu|flag_reg~17 ; 1 ;; light8080:cpu|flag_reg~16 ; 1 ;; light8080:cpu|flag_reg~15 ; 1 ;; light8080:cpu|flag_reg~14 ; 1 ;; light8080:cpu|T2~10 ; 1 ;; light8080:cpu|T2~9 ; 1 ;; light8080:cpu|T2~8 ; 1 ;; light8080:cpu|T2~7 ; 1 ;; light8080:cpu|T1~10 ; 1 ;; light8080:cpu|T2~6 ; 1 ;; light8080:cpu|T1~9 ; 1 ;; light8080:cpu|T2~5 ; 1 ;; light8080:cpu|T1~8 ; 1 ;; light8080:cpu|T1~7 ; 1 ;; light8080:cpu|T1~6 ; 1 ;; light8080:cpu|T2~4 ; 1 ;; intr_ctrl:intrc|intSel~15 ; 1 ;; intr_ctrl:intrc|Selector1~0 ; 1 ;; intr_ctrl:intrc|intSel~14 ; 1 ;; rxfull~0 ; 1 ;; light8080:cpu|flag_reg[7]~13 ; 1 ;; light8080:cpu|flag_reg~12 ; 1 ;; light8080:cpu|flag_reg~11 ; 1 ;; light8080:cpu|flag_reg~9 ; 1 ;; light8080:cpu|flag_reg~8 ; 1 ;; light8080:cpu|flag_reg~7 ; 1 ;; light8080:cpu|int_pending~1 ; 1 ;; light8080:cpu|int_pending~0 ; 1 ;; uart:uart|rxShiftReg[0] ; 1 ;; light8080:cpu|T1~5 ; 1 ;; light8080:cpu|T1~4 ; 1 ;; light8080:cpu|Equal2~0 ; 1 ;; light8080:cpu|reg_aux_cy~0 ; 1 ;; light8080:cpu|Equal13~1 ; 1 ;; light8080:cpu|T2~2 ; 1 ;; light8080:cpu|T1~2 ; 1 ;; light8080:cpu|daa_res9~0 ; 1 ;; light8080:cpu|flag_reg~6 ; 1 ;; light8080:cpu|flag_reg~5 ; 1 ;; light8080:cpu|load_psw~0 ; 1 ;; light8080:cpu|flag_reg~4 ; 1 ;; light8080:cpu|flag_reg~3 ; 1 ;; light8080:cpu|flag_reg~2 ; 1 ;; uart:uart|txShiftReg~6 ; 1 ;; uart:uart|txShiftReg[4] ; 1 ;; light8080:cpu|data_output[7]~9 ; 1 ;; light8080:cpu|data_output[1]~8 ; 1 ;; light8080:cpu|Mux26~6 ; 1 ;; light8080:cpu|Mux24~7 ; 1 ;; light8080:cpu|Mux24~6 ; 1 ;; light8080:cpu|Mux24~4 ; 1 ;; light8080:cpu|Mux26~4 ; 1 ;; light8080:cpu|Mux26~2 ; 1 ;; light8080:cpu|Mux26~1 ; 1 ;; light8080:cpu|Mux25~9 ; 1 ;; light8080:cpu|Mux25~8 ; 1 ;; light8080:cpu|Mux25~5 ; 1 ;; light8080:cpu|Mux25~4 ; 1 ;; light8080:cpu|DO[4]~11 ; 1 ;; light8080:cpu|DO[4]~10 ; 1 ;; light8080:cpu|DO[4]~9 ; 1 ;; light8080:cpu|DO[4]~8 ; 1 ;; light8080:cpu|Mux22~2 ; 1 ;; light8080:cpu|Mux22~1 ; 1 ;; light8080:cpu|alu_mux1[5]~7 ; 1 ;; light8080:cpu|Mux14~0 ; 1 ;; light8080:cpu|Mux22~0 ; 1 ;; light8080:cpu|Mux21~2 ; 1 ;; light8080:cpu|Mux21~1 ; 1 ;; light8080:cpu|Mux21~0 ; 1 ;; light8080:cpu|alu_mux1[6]~6 ; 1 ;; light8080:cpu|Mux13~0 ; 1 ;; light8080:cpu|rbank~238 ; 1 ;; light8080:cpu|rbank~236 ; 1 ;; light8080:cpu|rbank~234 ; 1 ;; light8080:cpu|rbank~232 ; 1 ;; light8080:cpu|rbank~230 ; 1 ;; light8080:cpu|rbank~228 ; 1 ;; light8080:cpu|rbank~226 ; 1 ;; light8080:cpu|rbank~224 ; 1 ;; light8080:cpu|rbank~222 ; 1 ;; light8080:cpu|rbank~220 ; 1 ;; light8080:cpu|rbank~218 ; 1 ;; light8080:cpu|rbank~216 ; 1 ;; light8080:cpu|rbank~214 ; 1 ;; light8080:cpu|rbank~212 ; 1 ;; light8080:cpu|rbank~210 ; 1 ;; light8080:cpu|rbank~208 ; 1 ;; light8080:cpu|arith_op2_sgn[1]~7 ; 1 ;; light8080:cpu|arith_op2_sgn[2]~6 ; 1 ;; light8080:cpu|arith_op2_sgn[3]~5 ; 1 ;; light8080:cpu|arith_op2_sgn[5]~3 ; 1 ;; light8080:cpu|arith_op2_sgn[6]~2 ; 1 ;; light8080:cpu|arith_op2_sgn[7]~1 ; 1 ;; light8080:cpu|Mux20~1 ; 1 ;; light8080:cpu|alu_mux1[7]~5 ; 1 ;; light8080:cpu|alu_mux1[7]~4 ; 1 ;; light8080:cpu|alu_mux1[7]~3 ; 1 ;; light8080:cpu|Mux12~0 ; 1 ;; light8080:cpu|uc_ret_addr~8 ; 1 ;; io_dout~20 ; 1 ;; io_dout~19 ; 1 ;; uart:uart|rxData[7] ; 1 ;; light8080:cpu|uc_addr~7 ; 1 ;; light8080:cpu|uc_ret_addr~7 ; 1 ;; light8080:cpu|uc_addr~6 ; 1 ;; io_dout~18 ; 1 ;; io_dout~17 ; 1 ;; uart:uart|rxData[6] ; 1 ;; light8080:cpu|uc_ret_addr~6 ; 1 ;; intr_ctrl:intrc|Selector5~0 ; 1 ;; io_dout~16 ; 1 ;; io_dout~15 ; 1 ;; uart:uart|rxData[5] ; 1 ;; light8080:cpu|uc_addr~5 ; 1 ;; light8080:cpu|uc_ret_addr~5 ; 1 ;; light8080:cpu|uc_addr~4 ; 1 ;; intr_ctrl:intrc|Selector6~0 ; 1 ;; io_dout~14 ; 1 ;; uart:uart|rxData[4] ; 1 ;; io_dout~13 ; 1 ;; light8080:cpu|uc_ret_addr~4 ; 1 ;; light8080:cpu|uc_addr~3 ; 1 ;; io_dout~12 ; 1 ;; io_dout~11 ; 1 ;; uart:uart|rxData[3] ; 1 ;; io_dout~10 ; 1 ;; io_dout~9 ; 1 ;; uart:uart|rxData[2] ; 1 ;; light8080:cpu|uc_addr~2 ; 1 ;; light8080:cpu|uc_ret_addr~3 ; 1 ;; light8080:cpu|uc_ret_addr~2 ; 1 ;; io_dout~8 ; 1 ;; io_dout~7 ; 1 ;; uart:uart|rxData[1] ; 1 ;; light8080:cpu|uc_addr~1 ; 1 ;; light8080:cpu|uc_ret_addr~0 ; 1 ;; light8080:cpu|uc_addr~0 ; 1 ;; light8080:cpu|Mux28~2 ; 1 ;; light8080:cpu|Mux28~1 ; 1 ;; intr_ctrl:intrc|cpu_inst[0]~5 ; 1 ;; intr_ctrl:intrc|cpu_inst[0]~3 ; 1 ;; light8080:cpu|inta_reg~0 ; 1 ;; io_dout[4]~4 ; 1 ;; io_dout~3 ; 1 ;; uart:uart|rxData[0] ; 1 ;; io_dout~2 ; 1 ;; light8080:cpu|alu_mux1[0]~2 ; 1 ;; light8080:cpu|alu_mux1[0]~1 ; 1 ;; light8080:cpu|alu_mux1[0]~0 ; 1 ;; light8080:cpu|Mux19~0 ; 1 ;; light8080:cpu|Mux27~0 ; 1 ;; light8080:cpu|cy_in_gated ; 1 ;; light8080:cpu|ucode_field2[20] ; 1 ;; light8080:cpu|reg_aux_cy ; 1 ;; light8080:cpu|arith_op2_sgn[0]~0 ; 1 ;; light8080:cpu|daa_res9[0] ; 1 ;; uart:uart|txShiftReg~5 ; 1 ;; uart:uart|txShiftReg[3] ; 1 ;; light8080:cpu|addr_low~8 ; 1 ;; light8080:cpu|rbank~206 ; 1 ;; light8080:cpu|rbank~123 ; 1 ;; light8080:cpu|rbank~205 ; 1 ;; light8080:cpu|rbank~27 ; 1 ;; light8080:cpu|rbank~91 ; 1 ;; light8080:cpu|rbank~59 ; 1 ;; light8080:cpu|rbank~204 ; 1 ;; light8080:cpu|rbank~203 ; 1 ;; light8080:cpu|rbank~99 ; 1 ;; light8080:cpu|rbank~202 ; 1 ;; light8080:cpu|rbank~3 ; 1 ;; light8080:cpu|rbank~35 ; 1 ;; light8080:cpu|rbank~67 ; 1 ;; light8080:cpu|rbank~201 ; 1 ;; light8080:cpu|rbank~115 ; 1 ;; light8080:cpu|rbank~200 ; 1 ;; light8080:cpu|rbank~19 ; 1 ;; light8080:cpu|rbank~51 ; 1 ;; light8080:cpu|rbank~83 ; 1 ;; light8080:cpu|rbank~199 ; 1 ;; light8080:cpu|rbank~107 ; 1 ;; light8080:cpu|rbank~198 ; 1 ;; light8080:cpu|rbank~11 ; 1 ;; light8080:cpu|rbank~75 ; 1 ;; light8080:cpu|rbank~43 ; 1 ;; light8080:cpu|addr_low~7 ; 1 ;; light8080:cpu|rbank~196 ; 1 ;; light8080:cpu|rbank~121 ; 1 ;; light8080:cpu|rbank~195 ; 1 ;; light8080:cpu|rbank~25 ; 1 ;; light8080:cpu|rbank~57 ; 1 ;; light8080:cpu|rbank~89 ; 1 ;; light8080:cpu|rbank~194 ; 1 ;; light8080:cpu|rbank~193 ; 1 ;; light8080:cpu|rbank~97 ; 1 ;; light8080:cpu|rbank~192 ; 1 ;; light8080:cpu|rbank~1 ; 1 ;; light8080:cpu|rbank~65 ; 1 ;; light8080:cpu|rbank~33 ; 1 ;; light8080:cpu|rbank~191 ; 1 ;; light8080:cpu|rbank~105 ; 1 ;; light8080:cpu|rbank~190 ; 1 ;; light8080:cpu|rbank~9 ; 1 ;; light8080:cpu|rbank~41 ; 1 ;; light8080:cpu|rbank~73 ; 1 ;; light8080:cpu|rbank~189 ; 1 ;; light8080:cpu|rbank~113 ; 1 ;; light8080:cpu|rbank~188 ; 1 ;; light8080:cpu|rbank~17 ; 1 ;; light8080:cpu|rbank~81 ; 1 ;; light8080:cpu|rbank~49 ; 1 ;; light8080:cpu|addr_low~6 ; 1 ;; light8080:cpu|rbank~186 ; 1 ;; light8080:cpu|rbank~122 ; 1 ;; light8080:cpu|rbank~185 ; 1 ;; light8080:cpu|rbank~98 ; 1 ;; light8080:cpu|rbank~106 ; 1 ;; light8080:cpu|rbank~114 ; 1 ;; light8080:cpu|rbank~184 ; 1 ;; light8080:cpu|rbank~183 ; 1 ;; light8080:cpu|rbank~26 ; 1 ;; light8080:cpu|rbank~182 ; 1 ;; light8080:cpu|rbank~2 ; 1 ;; light8080:cpu|rbank~18 ; 1 ;; light8080:cpu|rbank~10 ; 1 ;; light8080:cpu|rbank~181 ; 1 ;; light8080:cpu|rbank~90 ; 1 ;; light8080:cpu|rbank~180 ; 1 ;; light8080:cpu|rbank~66 ; 1 ;; light8080:cpu|rbank~82 ; 1 ;; light8080:cpu|rbank~74 ; 1 ;; light8080:cpu|rbank~179 ; 1 ;; light8080:cpu|rbank~58 ; 1 ;; light8080:cpu|rbank~178 ; 1 ;; light8080:cpu|rbank~34 ; 1 ;; light8080:cpu|rbank~42 ; 1 ;; light8080:cpu|rbank~50 ; 1 ;; light8080:cpu|addr_low~5 ; 1 ;; light8080:cpu|rbank~176 ; 1 ;; light8080:cpu|rbank~120 ; 1 ;; light8080:cpu|rbank~175 ; 1 ;; light8080:cpu|rbank~96 ; 1 ;; light8080:cpu|rbank~112 ; 1 ;; light8080:cpu|rbank~104 ; 1 ;; light8080:cpu|rbank~174 ; 1 ;; light8080:cpu|rbank~173 ; 1 ;; light8080:cpu|rbank~24 ; 1 ;; light8080:cpu|rbank~172 ; 1 ;; light8080:cpu|rbank~0 ; 1 ;; light8080:cpu|rbank~8 ; 1 ;; light8080:cpu|rbank~16 ; 1 ;; light8080:cpu|rbank~171 ; 1 ;; light8080:cpu|rbank~56 ; 1 ;; light8080:cpu|rbank~170 ; 1 ;; light8080:cpu|rbank~32 ; 1 ;; light8080:cpu|rbank~48 ; 1 ;; light8080:cpu|rbank~40 ; 1 ;; light8080:cpu|rbank~169 ; 1 ;; light8080:cpu|rbank~88 ; 1 ;; light8080:cpu|rbank~168 ; 1 ;; light8080:cpu|rbank~64 ; 1 ;; light8080:cpu|rbank~72 ; 1 ;; light8080:cpu|rbank~80 ; 1 ;; light8080:cpu|addr_low~4 ; 1 ;; light8080:cpu|rbank~166 ; 1 ;; light8080:cpu|rbank~124 ; 1 ;; light8080:cpu|rbank~165 ; 1 ;; light8080:cpu|rbank~100 ; 1 ;; light8080:cpu|rbank~116 ; 1 ;; light8080:cpu|rbank~108 ; 1 ;; light8080:cpu|rbank~164 ; 1 ;; light8080:cpu|rbank~163 ; 1 ;; light8080:cpu|rbank~28 ; 1 ;; light8080:cpu|rbank~162 ; 1 ;; light8080:cpu|rbank~4 ; 1 ;; light8080:cpu|rbank~12 ; 1 ;; light8080:cpu|rbank~20 ; 1 ;; light8080:cpu|rbank~161 ; 1 ;; light8080:cpu|rbank~60 ; 1 ;; light8080:cpu|rbank~160 ; 1 ;; light8080:cpu|rbank~36 ; 1 ;; light8080:cpu|rbank~52 ; 1 ;; light8080:cpu|rbank~44 ; 1 ;; light8080:cpu|rbank~159 ; 1 ;; light8080:cpu|rbank~92 ; 1 ;; light8080:cpu|rbank~158 ; 1 ;; light8080:cpu|rbank~68 ; 1 ;; light8080:cpu|rbank~76 ; 1 ;; light8080:cpu|rbank~84 ; 1 ;; light8080:cpu|addr_low~3 ; 1 ;; light8080:cpu|rbank~156 ; 1 ;; light8080:cpu|rbank~125 ; 1 ;; light8080:cpu|rbank~155 ; 1 ;; light8080:cpu|rbank~29 ; 1 ;; light8080:cpu|rbank~61 ; 1 ;; light8080:cpu|rbank~93 ; 1 ;; light8080:cpu|rbank~154 ; 1 ;; light8080:cpu|rbank~153 ; 1 ;; light8080:cpu|rbank~101 ; 1 ;; light8080:cpu|rbank~152 ; 1 ;; light8080:cpu|rbank~5 ; 1 ;; light8080:cpu|rbank~69 ; 1 ;; light8080:cpu|rbank~37 ; 1 ;; light8080:cpu|rbank~151 ; 1 ;; light8080:cpu|rbank~109 ; 1 ;; light8080:cpu|rbank~150 ; 1 ;; light8080:cpu|rbank~13 ; 1 ;; light8080:cpu|rbank~45 ; 1 ;; light8080:cpu|rbank~77 ; 1 ;; light8080:cpu|rbank~149 ; 1 ;; light8080:cpu|rbank~117 ; 1 ;; light8080:cpu|rbank~148 ; 1 ;; light8080:cpu|rbank~21 ; 1 ;; light8080:cpu|rbank~85 ; 1 ;; light8080:cpu|rbank~53 ; 1 ;; light8080:cpu|addr_low~2 ; 1 ;; light8080:cpu|rbank~146 ; 1 ;; light8080:cpu|rbank~126 ; 1 ;; light8080:cpu|rbank~145 ; 1 ;; light8080:cpu|rbank~102 ; 1 ;; light8080:cpu|rbank~110 ; 1 ;; light8080:cpu|rbank~118 ; 1 ;; light8080:cpu|rbank~144 ; 1 ;; light8080:cpu|rbank~143 ; 1 ;; light8080:cpu|rbank~30 ; 1 ;; light8080:cpu|rbank~142 ; 1 ;; light8080:cpu|rbank~6 ; 1 ;; light8080:cpu|rbank~22 ; 1 ;; light8080:cpu|rbank~14 ; 1 ;; light8080:cpu|rbank~141 ; 1 ;; light8080:cpu|rbank~94 ; 1 ;; light8080:cpu|rbank~140 ; 1 ;; light8080:cpu|rbank~70 ; 1 ;; light8080:cpu|rbank~86 ; 1 ;; light8080:cpu|rbank~78 ; 1 ;; light8080:cpu|rbank~139 ; 1 ;; light8080:cpu|rbank~62 ; 1 ;; light8080:cpu|rbank~138 ; 1 ;; light8080:cpu|rbank~38 ; 1 ;; light8080:cpu|rbank~46 ; 1 ;; light8080:cpu|rbank~54 ; 1 ;; light8080:cpu|addr_low~0 ; 1 ;; light8080:cpu|rbank~136 ; 1 ;; light8080:cpu|rbank~127 ; 1 ;; light8080:cpu|rbank~135 ; 1 ;; light8080:cpu|rbank~31 ; 1 ;; light8080:cpu|rbank~95 ; 1 ;; light8080:cpu|rbank~63 ; 1 ;; light8080:cpu|rbank~134 ; 1 ;; light8080:cpu|rbank~133 ; 1 ;; light8080:cpu|rbank~103 ; 1 ;; light8080:cpu|rbank~132 ; 1 ;; light8080:cpu|rbank~7 ; 1 ;; light8080:cpu|rbank~39 ; 1 ;; light8080:cpu|rbank~71 ; 1 ;; light8080:cpu|Mux10~0 ; 1 ;; light8080:cpu|IR[1] ; 1 ;; light8080:cpu|rbank~131 ; 1 ;; light8080:cpu|rbank~119 ; 1 ;; light8080:cpu|rbank~130 ; 1 ;; light8080:cpu|rbank~23 ; 1 ;; light8080:cpu|rbank~55 ; 1 ;; light8080:cpu|rbank~87 ; 1 ;; light8080:cpu|Mux11~0 ; 1 ;; light8080:cpu|IR[0] ; 1 ;; light8080:cpu|rbank~129 ; 1 ;; light8080:cpu|rbank~111 ; 1 ;; light8080:cpu|rbank~128 ; 1 ;; light8080:cpu|rbank~15 ; 1 ;; light8080:cpu|Mux8~0 ; 1 ;; light8080:cpu|rbank~79 ; 1 ;; light8080:cpu|Mux9~0 ; 1 ;; light8080:cpu|IR[2] ; 1 ;; light8080:cpu|rbank~47 ; 1 ;; light8080:cpu|Mux0~6 ; 1 ;; light8080:cpu|uc_ret_addr[7] ; 1 ;; cpu_din[7]~14 ; 1 ;; io_dout[7] ; 1 ;; light8080:cpu|uc_addr[7] ; 1 ;; light8080:cpu|Mux1~4 ; 1 ;; light8080:cpu|uc_ret_addr[6] ; 1 ;; light8080:cpu|uc_addr[6] ; 1 ;; cpu_din[6]~12 ; 1 ;; io_dout[6] ; 1 ;; light8080:cpu|Mux2~4 ; 1 ;; light8080:cpu|uc_ret_addr[5] ; 1 ;; intr_ctrl:intrc|cpu_inst[5] ; 1 ;; cpu_din[5]~10 ; 1 ;; io_dout[5] ; 1 ;; light8080:cpu|uc_addr[5] ; 1 ;; light8080:cpu|Mux3~4 ; 1 ;; light8080:cpu|uc_ret_addr[4] ; 1 ;; light8080:cpu|uc_addr[4] ; 1 ;; intr_ctrl:intrc|cpu_inst[4] ; 1 ;; cpu_din[4]~8 ; 1 ;; io_dout[4] ; 1 ;; light8080:cpu|Mux4~4 ; 1 ;; light8080:cpu|uc_ret_addr[3] ; 1 ;; light8080:cpu|uc_addr[3] ; 1 ;; cpu_din[3]~6 ; 1 ;; io_dout[3] ; 1 ;; light8080:cpu|Mux5~7 ; 1 ;; light8080:cpu|uc_do_jmp~1 ; 1 ;; cpu_din[2]~4 ; 1 ;; io_dout[2] ; 1 ;; light8080:cpu|Mux5~5 ; 1 ;; light8080:cpu|Mux5~4 ; 1 ;; light8080:cpu|uc_addr[2] ; 1 ;; light8080:cpu|uc_ret_addr[2] ; 1 ;; light8080:cpu|Mux6~4 ; 1 ;; light8080:cpu|uc_ret_addr[1] ; 1 ;; cpu_din[1]~2 ; 1 ;; io_dout[1] ; 1 ;; light8080:cpu|uc_addr[1] ; 1 ;; light8080:cpu|Mux7~4 ; 1 ;; light8080:cpu|uc_ret_addr[0] ; 1 ;; light8080:cpu|uc_addr[0] ; 1 ;; cpu_din[0]~0 ; 1 ;; io_dout[0] ; 1 ;; uart:uart|txShiftReg~3 ; 1 ;; uart:uart|txShiftReg[2] ; 1 ;; p2dir[7] ; 1 ;; p2reg[7] ; 1 ;; p2dir[6] ; 1 ;; p2reg[6] ; 1 ;; p2dir[5] ; 1 ;; p2reg[5] ; 1 ;; p2dir[4] ; 1 ;; p2reg[4] ; 1 ;; p2dir[3] ; 1 ;; p2reg[3] ; 1 ;; p2dir[2] ; 1 ;; p2reg[2] ; 1 ;; p2dir[1] ; 1 ;; p2reg[1] ; 1 ;; p2dir[0] ; 1 ;; p2reg[0] ; 1 ;; p1dir[7] ; 1 ;; p1reg[7] ; 1 ;; p1dir[6] ; 1 ;; p1reg[6] ; 1 ;; p1dir[5] ; 1 ;; p1reg[5] ; 1 ;; p1dir[4] ; 1 ;; p1reg[4] ; 1 ;; p1dir[3] ; 1 ;; p1reg[3] ; 1 ;; p1dir[2] ; 1 ;; p1reg[2] ; 1 ;; p1dir[1] ; 1 ;; p1reg[1] ; 1 ;; p1dir[0] ; 1 ;; p1reg[0] ; 1 ;; uart:uart|txBusy~2 ; 1 ;; uart:uart|txBusy~1 ; 1 ;; uart:uart|txBusy~0 ; 1 ;; uart:uart|Equal5~9 ; 1 ;; uart:uart|Equal5~8 ; 1 ;; uartbaud[15] ; 1 ;; uartbaud[14] ; 1 ;; uart:uart|Equal5~7 ; 1 ;; uartbaud[13] ; 1 ;; uartbaud[12] ; 1 ;; uart:uart|Equal5~6 ; 1 ;; uartbaud[11] ; 1 ;; uartbaud[10] ; 1 ;; uart:uart|Equal5~5 ; 1 ;; uartbaud[9] ; 1 ;; uartbaud[8] ; 1 ;; uart:uart|Equal5~4 ; 1 ;; uart:uart|Equal5~3 ; 1 ;; uartbaud[7] ; 1 ;; uartbaud[6] ; 1 ;; uart:uart|Equal5~2 ; 1 ;; uartbaud[5] ; 1 ;; uartbaud[4] ; 1 ;; uart:uart|Equal5~1 ; 1 ;; uartbaud[3] ; 1 ;; uartbaud[2] ; 1 ;; uart:uart|Equal5~0 ; 1 ;; uartbaud[1] ; 1 ;; uartbaud[0] ; 1 ;; uart:uart|txShiftReg~1 ; 1 ;; uart:uart|txShiftReg[1] ; 1 ;; uart:uart|serOut~0 ; 1 ;; uart:uart|txShiftReg[0] ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a14 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a9 ; 1 ;; uart:uart|rxBitCnt[3]~10 ; 1 ;; uart:uart|rxBitCnt[2]~9 ; 1 ;; uart:uart|rxBitCnt[2]~8 ; 1 ;; uart:uart|rxBitCnt[1]~7 ; 1 ;; uart:uart|rxBitCnt[1]~6 ; 1 ;; uart:uart|rxBitCnt[0]~5 ; 1 ;; uart:uart|rxBitCnt[0]~4 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a7 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a8 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a15 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a16 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a22 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a23 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a24 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a6 ; 1 ;; light8080:cpu|Add3~12 ; 1 ;; light8080:cpu|Add3~11 ; 1 ;; light8080:cpu|Add3~10 ; 1 ;; light8080:cpu|Add3~9 ; 1 ;; light8080:cpu|Add3~8 ; 1 ;; light8080:cpu|Add3~7 ; 1 ;; light8080:cpu|Add3~6 ; 1 ;; light8080:cpu|Add3~5 ; 1 ;; light8080:cpu|Add3~4 ; 1 ;; light8080:cpu|Add3~3 ; 1 ;; light8080:cpu|Add3~2 ; 1 ;; light8080:cpu|Add3~1 ; 1 ;; light8080:cpu|Add3~0 ; 1 ;; light8080:cpu|daa_res9[3] ; 1 ;; light8080:cpu|daa_res9[2] ; 1 ;; light8080:cpu|daa_res9[4] ; 1 ;; light8080:cpu|Add1~17 ; 1 ;; light8080:cpu|Add1~16 ; 1 ;; light8080:cpu|Add1~15 ; 1 ;; light8080:cpu|Add1~14 ; 1 ;; light8080:cpu|Add1~13 ; 1 ;; light8080:cpu|Add1~12 ; 1 ;; light8080:cpu|Add1~11 ; 1 ;; light8080:cpu|Add1~10 ; 1 ;; light8080:cpu|Add1~9 ; 1 ;; light8080:cpu|Add1~8 ; 1 ;; light8080:cpu|Add1~7 ; 1 ;; light8080:cpu|Add1~6 ; 1 ;; light8080:cpu|Add1~5 ; 1 ;; light8080:cpu|Add1~4 ; 1 ;; light8080:cpu|daa_res9[7] ; 1 ;; light8080:cpu|Add1~3 ; 1 ;; light8080:cpu|Add1~2 ; 1 ;; light8080:cpu|Add1~1 ; 1 ;; uart:uart|txBitCnt[3]~11 ; 1 ;; uart:uart|txBitCnt[2]~10 ; 1 ;; uart:uart|txBitCnt[2]~9 ; 1 ;; uart:uart|txBitCnt[1]~8 ; 1 ;; uart:uart|txBitCnt[1]~7 ; 1 ;; uart:uart|txBitCnt[0]~5 ; 1 ;; uart:uart|txBitCnt[0]~4 ; 1 ;; uart:uart|baudCount[15]~46 ; 1 ;; uart:uart|baudCount[14]~45 ; 1 ;; uart:uart|baudCount[14]~44 ; 1 ;; uart:uart|baudCount[13]~43 ; 1 ;; uart:uart|baudCount[13]~42 ; 1 ;; uart:uart|baudCount[12]~41 ; 1 ;; uart:uart|baudCount[12]~40 ; 1 ;; uart:uart|baudCount[11]~39 ; 1 ;; uart:uart|baudCount[11]~38 ; 1 ;; uart:uart|baudCount[10]~37 ; 1 ;; uart:uart|baudCount[10]~36 ; 1 ;; uart:uart|baudCount[9]~35 ; 1 ;; uart:uart|baudCount[9]~34 ; 1 ;; uart:uart|baudCount[8]~33 ; 1 ;; uart:uart|baudCount[8]~32 ; 1 ;; uart:uart|baudCount[7]~31 ; 1 ;; uart:uart|baudCount[7]~30 ; 1 ;; uart:uart|baudCount[6]~29 ; 1 ;; uart:uart|baudCount[6]~28 ; 1 ;; uart:uart|baudCount[5]~27 ; 1 ;; uart:uart|baudCount[5]~26 ; 1 ;; uart:uart|baudCount[4]~25 ; 1 ;; uart:uart|baudCount[4]~24 ; 1 ;; uart:uart|baudCount[3]~23 ; 1 ;; uart:uart|baudCount[3]~22 ; 1 ;; uart:uart|baudCount[2]~21 ; 1 ;; uart:uart|baudCount[2]~20 ; 1 ;; uart:uart|baudCount[1]~19 ; 1 ;; uart:uart|baudCount[1]~18 ; 1 ;; uart:uart|baudCount[0]~17 ; 1 ;; uart:uart|baudCount[0]~16 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a7 ; 1 ;; light8080:cpu|addr_plus_1[6]~13 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a6 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a5 ; 1 ;; light8080:cpu|addr_plus_1[5]~11 ; 1 ;; light8080:cpu|addr_plus_1[4]~9 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a4 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a10 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a11 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a17 ; 1 ;; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ram_block1a18 ; 1 ;; light8080:cpu|addr_plus_1[3]~7 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a3 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a2 ; 1 ;; light8080:cpu|addr_plus_1[2]~5 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a1 ; 1 ;; light8080:cpu|addr_plus_1[1]~3 ; 1 ;; light8080:cpu|addr_plus_1[0]~1 ; 1 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ram_block1a0 ; 1 ;; uart:uart|txBaudCnt[3]~10 ; 1 ;; uart:uart|txBaudCnt[2]~9 ; 1 ;; uart:uart|txBaudCnt[2]~8 ; 1 ;; uart:uart|txBaudCnt[1]~7 ; 1 ;; uart:uart|txBaudCnt[1]~6 ; 1 ;; uart:uart|txBaudCnt[0]~5 ; 1 ;; uart:uart|txBaudCnt[0]~4 ; 1 ;+------------------------------------------------------------------------------------------------+---------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary ;+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+; light8080:cpu|micro_rom:rom|altsyncram:Ram0_rtl_0|altsyncram_ts61:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 512 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 512 ; 29 ; -- ; -- ; 14848 ; 4 ; db/l80soc.rom0_micro_rom_cd0ab125.hdl.mif ; M4K_X27_Y16, M4K_X27_Y13, M4K_X27_Y17, M4K_X27_Y18 ;; ram_image:ram|altsyncram:ram_rtl_0|altsyncram_tv81:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 4096 ; 8 ; -- ; -- ; yes ; no ; -- ; -- ; 32768 ; 4096 ; 8 ; -- ; -- ; 32768 ; 8 ; db/l80soc.ram0_ram_image_778cd75f.hdl.mif ; M4K_X27_Y15, M4K_X27_Y12, M4K_X27_Y10, M4K_X27_Y14, M4K_X27_Y11, M4K_X27_Y9, M4K_X27_Y8, M4K_X27_Y7 ;+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------------------+-----------------------------------------------------------------------------------------------------+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.+-----------------------------------------------------+; Interconnect Usage Summary ;+----------------------------+------------------------+; Interconnect Resource Type ; Usage ;+----------------------------+------------------------+; Block interconnects ; 1,103 / 26,052 ( 4 % ) ;; C16 interconnects ; 9 / 1,156 ( < 1 % ) ;; C4 interconnects ; 602 / 17,952 ( 3 % ) ;; Direct links ; 140 / 26,052 ( < 1 % ) ;; Global clocks ; 2 / 8 ( 25 % ) ;; Local interconnects ; 299 / 8,256 ( 4 % ) ;; R24 interconnects ; 8 / 1,020 ( < 1 % ) ;; R4 interconnects ; 481 / 22,440 ( 2 % ) ;+----------------------------+------------------------++----------------------------------------------------------------------------+; LAB Logic Elements ;+---------------------------------------------+------------------------------+; Number of Logic Elements (Average = 12.37) ; Number of LABs (Total = 51) ;+---------------------------------------------+------------------------------+; 1 ; 2 ;; 2 ; 2 ;; 3 ; 0 ;; 4 ; 0 ;; 5 ; 3 ;; 6 ; 1 ;; 7 ; 0 ;; 8 ; 3 ;; 9 ; 1 ;; 10 ; 1 ;; 11 ; 2 ;; 12 ; 3 ;; 13 ; 2 ;; 14 ; 7 ;; 15 ; 5 ;; 16 ; 19 ;+---------------------------------------------+------------------------------++-------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+------------------------------+; LAB-wide Signals (Average = 1.78) ; Number of LABs (Total = 51) ;+------------------------------------+------------------------------+; 1 Async. clear ; 16 ;; 1 Clock ; 47 ;; 1 Clock enable ; 12 ;; 1 Sync. clear ; 7 ;; 1 Sync. load ; 1 ;; 2 Clock enables ; 8 ;+------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+------------------------------+; Number of Signals Sourced (Average = 18.61) ; Number of LABs (Total = 51) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 1 ;; 2 ; 3 ;; 3 ; 0 ;; 4 ; 0 ;; 5 ; 0 ;; 6 ; 1 ;; 7 ; 1 ;; 8 ; 1 ;; 9 ; 0 ;; 10 ; 0 ;; 11 ; 0 ;; 12 ; 2 ;; 13 ; 0 ;; 14 ; 4 ;; 15 ; 2 ;; 16 ; 2 ;; 17 ; 1 ;; 18 ; 1 ;; 19 ; 3 ;; 20 ; 5 ;; 21 ; 5 ;; 22 ; 5 ;; 23 ; 1 ;; 24 ; 3 ;; 25 ; 3 ;; 26 ; 0 ;; 27 ; 2 ;; 28 ; 1 ;; 29 ; 2 ;; 30 ; 1 ;; 31 ; 0 ;; 32 ; 1 ;+----------------------------------------------+------------------------------++--------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+------------------------------+; Number of Signals Sourced Out (Average = 8.88) ; Number of LABs (Total = 51) ;+-------------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 3 ;; 2 ; 3 ;; 3 ; 2 ;; 4 ; 3 ;; 5 ; 3 ;; 6 ; 3 ;; 7 ; 1 ;; 8 ; 4 ;; 9 ; 1 ;; 10 ; 6 ;; 11 ; 7 ;; 12 ; 3 ;; 13 ; 3 ;; 14 ; 5 ;; 15 ; 1 ;; 16 ; 3 ;+-------------------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+------------------------------+; Number of Distinct Inputs (Average = 18.25) ; Number of LABs (Total = 51) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 0 ;; 3 ; 2 ;; 4 ; 0 ;; 5 ; 2 ;; 6 ; 1 ;; 7 ; 4 ;; 8 ; 1 ;; 9 ; 0 ;; 10 ; 1 ;; 11 ; 1 ;; 12 ; 1 ;; 13 ; 1 ;; 14 ; 3 ;; 15 ; 3 ;; 16 ; 1 ;; 17 ; 1 ;; 18 ; 1 ;; 19 ; 2 ;; 20 ; 1 ;; 21 ; 2 ;; 22 ; 3 ;; 23 ; 2 ;; 24 ; 5 ;; 25 ; 2 ;; 26 ; 5 ;; 27 ; 1 ;; 28 ; 1 ;; 29 ; 1 ;; 30 ; 0 ;; 31 ; 3 ;+----------------------------------------------+------------------------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Active Serial ;; Error detection CRC ; Off ;; nCEO ; As output driving ground ;; ASDO,nCSO ; As input tri-stated ;; Reserve all unused pins ; As output driving ground ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II 32-bit FitterInfo: Version 11.1 Build 173 11/01/2011 SJ Web EditionInfo: Processing started: Sun Apr 29 15:05:36 2012Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off l80soc -c l80socWarning (20028): Parallel compilation is not licensed and has been disabledInfo (119006): Selected device EP2C8Q208C8 for design "l80soc"Info (21077): Low junction temperature is 0 degrees CInfo (21077): High junction temperature is 85 degrees CInfo (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo (176445): Device EP2C5Q208C8 is compatibleInfo (176445): Device EP2C5Q208I8 is compatibleInfo (176445): Device EP2C8Q208I8 is compatibleInfo (169124): Fitter converted 3 user pins into dedicated programming pinsInfo (169125): Pin ~ASDO~ is reserved at location 1Info (169125): Pin ~nCSO~ is reserved at location 2Info (169125): Pin ~LVDS54p/nCEO~ is reserved at location 108Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Critical Warning (169085): No exact pin location assignment(s) for 24 pins of 24 total pinsInfo (169086): Pin p1dio[0] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[1] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[2] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[3] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[4] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[5] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[6] not assigned to an exact location on the deviceInfo (169086): Pin p1dio[7] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[0] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[1] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[2] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[3] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[4] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[5] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[6] not assigned to an exact location on the deviceInfo (169086): Pin p2dio[7] not assigned to an exact location on the deviceInfo (169086): Pin txd not assigned to an exact location on the deviceInfo (169086): Pin clock not assigned to an exact location on the deviceInfo (169086): Pin reset not assigned to an exact location on the deviceInfo (169086): Pin extint[1] not assigned to an exact location on the deviceInfo (169086): Pin extint[3] not assigned to an exact location on the deviceInfo (169086): Pin extint[2] not assigned to an exact location on the deviceInfo (169086): Pin extint[0] not assigned to an exact location on the deviceInfo (169086): Pin rxd not assigned to an exact location on the deviceCritical Warning (332012): Synopsys Design Constraints File file not found: 'l80soc.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.Info (336004): TimeQuest will use the Classic Timing Analyzer's FMAX_REQUIREMENT assignment (or --fmax command-line argument) as default timing requirement. Any other Classic Timing Analyzer assignment will be ignored.Info (332144): No user constrained base clocks found in the designInfo (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirementsInfo (332111): Found 1 clocksInfo (332111): Period Clock NameInfo (332111): ======== ============Info (332111): 1.000 clockInfo (176353): Automatically promoted node clock (placed in PIN 23 (CLK0, LVDSCLK0p, Input))Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2Info (176353): Automatically promoted node reset (placed in PIN 24 (CLK1, LVDSCLK0n, Input))Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1Info (176356): Following destination nodes may be non-global or may not use global or regional clocksInfo (176357): Destination node light8080:cpu|inte_regInfo (176357): Destination node light8080:cpu|inta_regInfo (176357): Destination node light8080:cpu|condition_regInfo (176357): Destination node light8080:cpu|delayed_eiInfo (176357): Destination node light8080:cpu|int_pendingInfo (176357): Destination node light8080:cpu|flag_reg[0]Info (176357): Destination node light8080:cpu|flag_reg[6]Info (176357): Destination node light8080:cpu|flag_reg[2]Info (176357): Destination node light8080:cpu|daa_res9[1]Info (176357): Destination node light8080:cpu|daa_res9[2]Info (176358): Non-global destination nodes limited to 10 nodesInfo (176233): Starting register packingExtra Info (176273): Performing register packing on registers with non-logic cell location assignmentsExtra Info (176274): Completed register packing on registers with non-logic cell location assignmentsExtra Info (176236): Started Fast Input/Output/OE register processingExtra Info (176237): Finished Fast Input/Output/OE register processingExtra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and densityExtra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocksInfo (176235): Finished register packingExtra Info (176219): No registers were packed into other blocksInfo (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placementInfo (176211): Number of I/O pins in group: 22 (unused VREF, 3.3V VCCIO, 5 input, 1 output, 16 bidirectional)Info (176212): I/O standards used: 3.3-V LVTTL.Info (176215): I/O bank details before I/O pin placementInfo (176214): Statistics of I/O banksInfo (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 28 pins availableInfo (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins availableInfo (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 34 pins availableInfo (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 36 pins availableInfo (171121): Fitter preparation operations ending: elapsed time is 00:00:04Info (170189): Fitter placement preparation operations beginningInfo (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02Info (170191): Fitter placement operations beginningInfo (170137): Fitter placement was successfulInfo (170192): Fitter placement operations ending: elapsed time is 00:00:07Info (170193): Fitter routing operations beginningInfo (170195): Router estimated average interconnect usage is 2% of the available device resourcesInfo (170196): Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19Info (170194): Fitter routing operations ending: elapsed time is 00:00:04Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info (170201): Optimizations that may affect the design's routability were skippedInfo (306004): Started post-fitting delay annotationWarning (306006): Found 17 output pins without output pin load capacitance assignmentInfo (306007): Pin "p1dio[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p1dio[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "p2dio[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306007): Pin "txd" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo (306005): Delay annotation completed successfullyInfo (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.Info: Quartus II 32-bit Fitter was successful. 0 errors, 6 warningsInfo: Peak virtual memory: 350 megabytesInfo: Processing ended: Sun Apr 29 15:06:10 2012Info: Elapsed time: 00:00:34Info: Total CPU time (on all processors): 00:00:23