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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (02/21/2012 - 11:58:43)</B></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD>xilinx_s3.ise</TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD>Placed and Routed</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD>l80soc</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD> No Errors</TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD>xc3s200-4ft256</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>33 Warnings</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.4</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> <TD> <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.unroutes'>All Signals Completely Routed</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD>Balanced</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> <TD> <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> <TD>Xilinx Default (unlocked)</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> <TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0) <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#FFFF99'> <TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD> <TD ALIGN=RIGHT>211</TD> <TD ALIGN=RIGHT>3,840</TD> <TD ALIGN=RIGHT>5%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> <TD ALIGN=RIGHT>327</TD> <TD ALIGN=RIGHT>3,840</TD> <TD ALIGN=RIGHT>8%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> <TD ALIGN=RIGHT>223</TD> <TD ALIGN=RIGHT>1,920</TD> <TD ALIGN=RIGHT>11%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD> <TD ALIGN=RIGHT>223</TD> <TD ALIGN=RIGHT>223</TD> <TD ALIGN=RIGHT>100%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD> <TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>223</TD> <TD ALIGN=RIGHT>0%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD> <TD ALIGN=RIGHT>328</TD> <TD ALIGN=RIGHT>3,840</TD> <TD ALIGN=RIGHT>8%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> <TD ALIGN=RIGHT>311</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD> <TD ALIGN=RIGHT>1</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used for Dual Port RAMs</TD> <TD ALIGN=RIGHT>16</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> <TD ALIGN=RIGHT>20</TD> <TD ALIGN=RIGHT>173</TD> <TD ALIGN=RIGHT>11%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD> <TD ALIGN=RIGHT>3</TD> <TD ALIGN=RIGHT>12</TD> <TD ALIGN=RIGHT>25%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD> <TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>8</TD> <TD ALIGN=RIGHT>12%</TD> <TD COLSPAN='2'> </TD> </TR> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> <TD ALIGN=RIGHT>3.29</TD> <TD> </TD> <TD> </TD> <TD COLSPAN='2'> </TD> </TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> <TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD> <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> <TD COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.unroutes'>All Signals Completely Routed</A></TD> <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> <TD COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> <TD> <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> <TD BGCOLOR='#FFFF99'><B> </B></TD> <TD COLSPAN='2'> </TD> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:54:55 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>31 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>6 Infos</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:21 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:29 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:40 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue Feb 21 11:58:43 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR> <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> </TABLE> <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> </TABLE> <br><center><b>Date Generated:</b> 02/21/2012 - 11:58:43</center> </BODY></HTML>
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