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# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# File: C:\altera\Kits\CycloneII_Starter_Kit-v1.0.0\proyectos\demo_tutorial\pin_assignment\c2sb_demo.csv
# Generated on: Sun Jul 19 05:05:49 2009

# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus II software.

To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Group,Current Strength,PCB layer
buttons[3],Input,PIN_T21,6,B6_N0,,,buttons[3..0],,
buttons[2],Input,PIN_T22,6,B6_N0,,,buttons[3..0],,
buttons[1],Input,PIN_R21,6,B6_N0,,,buttons[3..0],,
buttons[0],Input,PIN_R22,6,B6_N0,,,buttons[3..0],,
flash_addr[21],Output,PIN_R13,7,B7_N0,,,flash_addr[21..0],,
flash_addr[20],Output,PIN_U13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[19],Output,PIN_V14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[18],Output,PIN_U14,7,B7_N0,,,flash_addr[21..0],,
flash_addr[17],Output,PIN_AA20,7,B7_N0,,,flash_addr[21..0],,
flash_addr[16],Output,PIN_AB12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[15],Output,PIN_AA12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[14],Output,PIN_AB13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[13],Output,PIN_AA13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[12],Output,PIN_AB14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[11],Output,PIN_T12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[10],Output,PIN_R12,7,B7_N1,,,flash_addr[21..0],,
flash_addr[9],Output,PIN_Y13,7,B7_N1,,,flash_addr[21..0],,
flash_addr[8],Output,PIN_R14,7,B7_N0,,,flash_addr[21..0],,
flash_addr[7],Output,PIN_W15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[6],Output,PIN_V15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[5],Output,PIN_U15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[4],Output,PIN_T15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[3],Output,PIN_R15,7,B7_N0,,,flash_addr[21..0],,
flash_addr[2],Output,PIN_Y16,7,B7_N0,,,flash_addr[21..0],,
flash_addr[1],Output,PIN_AA14,7,B7_N1,,,flash_addr[21..0],,
flash_addr[0],Output,PIN_AB20,7,B7_N0,,,flash_addr[21..0],,
flash_data[7],Input,PIN_AA19,7,B7_N0,,,flash_data[7..0],,
flash_data[6],Input,PIN_AB19,7,B7_N0,,,flash_data[7..0],,
flash_data[5],Input,PIN_AA18,7,B7_N0,,,flash_data[7..0],,
flash_data[4],Input,PIN_AB18,7,B7_N0,,,flash_data[7..0],,
flash_data[3],Input,PIN_AA17,7,B7_N1,,,flash_data[7..0],,
flash_data[2],Input,PIN_AB17,7,B7_N1,,,flash_data[7..0],,
flash_data[1],Input,PIN_AA16,7,B7_N1,,,flash_data[7..0],,
flash_data[0],Input,PIN_AB16,7,B7_N1,,,flash_data[7..0],,
flash_oe_n,Output,PIN_AA15,7,B7_N1,,,,,
flash_reset_n,Output,PIN_W14,7,B7_N1,,,,,
flash_we_n,Output,PIN_Y14,7,B7_N0,,,,,
green_leds[7],Output,PIN_Y21,6,B6_N1,,,green_leds[7..0],,
green_leds[6],Output,PIN_Y22,6,B6_N1,,,green_leds[7..0],,
green_leds[5],Output,PIN_W21,6,B6_N1,,,green_leds[7..0],,
green_leds[4],Output,PIN_W22,6,B6_N1,,,green_leds[7..0],,
green_leds[3],Output,PIN_V21,6,B6_N1,,,green_leds[7..0],,
green_leds[2],Output,PIN_V22,6,B6_N1,,,green_leds[7..0],,
green_leds[1],Output,PIN_U21,6,B6_N1,,,green_leds[7..0],,
green_leds[0],Output,PIN_U22,6,B6_N1,,,green_leds[7..0],,
hex0[0],Output,PIN_J2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[1],Output,PIN_J1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[2],Output,PIN_H2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[3],Output,PIN_H1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[4],Output,PIN_F2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[5],Output,PIN_F1,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex0[6],Output,PIN_E2,2,B2_N1,3.3-V LVTTL,,hex0[0..6],,
hex1[0],Output,PIN_E1,2,B2_N1,3.3-V LVTTL,,hex1[0..6],,
hex1[1],Output,PIN_H6,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[2],Output,PIN_H5,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[3],Output,PIN_H4,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[4],Output,PIN_G3,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[5],Output,PIN_D2,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex1[6],Output,PIN_D1,2,B2_N0,3.3-V LVTTL,,hex1[0..6],,
hex2[0],Output,PIN_G5,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[1],Output,PIN_G6,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[2],Output,PIN_C2,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[3],Output,PIN_C1,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[4],Output,PIN_E3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[5],Output,PIN_E4,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex2[6],Output,PIN_D3,2,B2_N0,3.3-V LVTTL,,hex2[0..6],,
hex3[0],Output,PIN_F4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[1],Output,PIN_D5,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[2],Output,PIN_D6,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[3],Output,PIN_J4,2,B2_N1,3.3-V LVTTL,,hex3[0..6],,
hex3[4],Output,PIN_L8,2,B2_N1,3.3-V LVTTL,,hex3[0..6],,
hex3[5],Output,PIN_F3,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
hex3[6],Output,PIN_D4,2,B2_N0,3.3-V LVTTL,,hex3[0..6],,
red_leds[9],Output,PIN_R17,6,B6_N1,,,red_leds[9..0],,
red_leds[8],Output,PIN_R18,6,B6_N0,,,red_leds[9..0],,
red_leds[7],Output,PIN_U18,6,B6_N1,,,red_leds[9..0],,
red_leds[6],Output,PIN_Y18,6,B6_N1,,,red_leds[9..0],,
red_leds[5],Output,PIN_V19,6,B6_N1,,,red_leds[9..0],,
red_leds[4],Output,PIN_T18,6,B6_N1,,,red_leds[9..0],,
red_leds[3],Output,PIN_Y19,6,B6_N1,,,red_leds[9..0],,
red_leds[2],Output,PIN_U19,6,B6_N1,,,red_leds[9..0],,
red_leds[1],Output,PIN_R19,6,B6_N0,,,red_leds[9..0],,
red_leds[0],Output,PIN_R20,6,B6_N0,,,red_leds[9..0],,
rxd,Input,PIN_F14,4,B4_N1,,,,,
sd_clk,Output,PIN_V20,6,B6_N1,,,,,
sd_cmd,Output,PIN_Y20,6,B6_N1,,,,,
sd_cs,Output,PIN_U20,6,B6_N1,,,,,
sd_data,Input,PIN_W20,6,B6_N1,,,,,
sram_addr[17],Output,PIN_Y5,8,B8_N1,,,sram_addr[17..0],,
sram_addr[16],Output,PIN_Y6,8,B8_N1,,,sram_addr[17..0],,
sram_addr[15],Output,PIN_T7,8,B8_N1,,,sram_addr[17..0],,
sram_addr[14],Output,PIN_R10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[13],Output,PIN_U10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[12],Output,PIN_Y10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[11],Output,PIN_T11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[10],Output,PIN_R11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[9],Output,PIN_W11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[8],Output,PIN_V11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[7],Output,PIN_AB11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[6],Output,PIN_AA11,8,B8_N0,,,sram_addr[17..0],,
sram_addr[5],Output,PIN_AB10,8,B8_N0,,,sram_addr[17..0],,
sram_addr[4],Output,PIN_AA5,8,B8_N1,,,sram_addr[17..0],,
sram_addr[3],Output,PIN_AB4,8,B8_N1,,,sram_addr[17..0],,
sram_addr[2],Output,PIN_AA4,8,B8_N1,,,sram_addr[17..0],,
sram_addr[1],Output,PIN_AB3,8,B8_N1,,,sram_addr[17..0],,
sram_addr[0],Output,PIN_AA3,8,B8_N1,,,sram_addr[17..0],,
sram_ce_n,Output,PIN_AB5,8,B8_N1,,,,,
sram_data[15],Bidir,PIN_U8,8,B8_N1,,,sram_data[15..0],,
sram_data[14],Bidir,PIN_V8,8,B8_N1,,,sram_data[15..0],,
sram_data[13],Bidir,PIN_W8,8,B8_N1,,,sram_data[15..0],,
sram_data[12],Bidir,PIN_R9,8,B8_N0,,,sram_data[15..0],,
sram_data[11],Bidir,PIN_U9,8,B8_N0,,,sram_data[15..0],,
sram_data[10],Bidir,PIN_V9,8,B8_N1,,,sram_data[15..0],,
sram_data[9],Bidir,PIN_W9,8,B8_N0,,,sram_data[15..0],,
sram_data[8],Bidir,PIN_Y9,8,B8_N0,,,sram_data[15..0],,
sram_data[7],Bidir,PIN_AB9,8,B8_N0,,,sram_data[15..0],,
sram_data[6],Bidir,PIN_AA9,8,B8_N0,,,sram_data[15..0],,
sram_data[5],Bidir,PIN_AB8,8,B8_N0,,,sram_data[15..0],,
sram_data[4],Bidir,PIN_AA8,8,B8_N0,,,sram_data[15..0],,
sram_data[3],Bidir,PIN_AB7,8,B8_N1,,,sram_data[15..0],,
sram_data[2],Bidir,PIN_AA7,8,B8_N1,,,sram_data[15..0],,
sram_data[1],Bidir,PIN_AB6,8,B8_N1,,,sram_data[15..0],,
sram_data[0],Bidir,PIN_AA6,8,B8_N1,,,sram_data[15..0],,
sram_lb_n,Output,PIN_Y7,8,B8_N1,,,,,
sram_oe_n,Output,PIN_T8,8,B8_N1,,,,,
sram_ub_n,Output,PIN_W7,8,B8_N1,,,,,
sram_we_n,Output,PIN_AA10,8,B8_N0,,,,,
switches[9],Input,PIN_L2,2,B2_N1,,,switches[9..0],,
switches[8],Input,PIN_M1,1,B1_N0,,,switches[9..0],,
switches[7],Input,PIN_M2,1,B1_N0,,,switches[9..0],,
switches[6],Input,PIN_U11,8,B8_N0,,,switches[9..0],,
switches[5],Input,PIN_U12,8,B8_N0,,,switches[9..0],,
switches[4],Input,PIN_W12,7,B7_N1,,,switches[9..0],,
switches[3],Input,PIN_V12,7,B7_N1,,,switches[9..0],,
switches[2],Input,PIN_M22,6,B6_N0,,,switches[9..0],,
switches[1],Input,PIN_L21,5,B5_N1,,,switches[9..0],,
switches[0],Input,PIN_L22,5,B5_N1,,,switches[9..0],,
txd,Output,PIN_G12,4,B4_N1,,,,,
clk_50MHz,Unknown,PIN_L1,2,B2_N1,,,,,