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[/] [loadbalancer/] [trunk/] [LB.map.summary] - Rev 2

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Analysis & Synthesis Status : Successful - Sun Jan 10 21:11:41 2010
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : LB
Top-level Entity Name : LB
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 523
    Dedicated logic registers : 870
Total registers : 870
Total pins : 145
Total virtual pins : 0
Total block memory bits : 154,560
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0

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