Subversion Repositories lwrisc

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file D:\LWRISC\SYN\ClaiRISC_core.prj
#-- Written on Mon Mar 10 17:43:02 2008


#add_file options
add_file -verilog "../RTL/sim_rom.v"
add_file -verilog "../RTL/test.v"
add_file -_include "../RTL/clairisc_def.h"
add_file -verilog "../RTL/mem_man.v"
add_file -verilog "../RTL/memory.v"
add_file -verilog "../RTL/risc_core.v"
add_file -_include "../RTL/rom_set.h"
add_file -verilog "../RTL/altera/rom512x12.v"
add_file -verilog "../RTL/altera/rom1024x12.v"
add_file -verilog "../RTL/altera/rom2048x12.v"
add_file -verilog "../RTL/altera/ram128x8.v"
add_file -verilog "../RTL/altera/rom32x12.v"
add_file -verilog "../RTL/altera/rom64x12.v"
add_file -verilog "../RTL/altera/rom128x12.v"
add_file -verilog "../RTL/altera/rom256x12.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package QC240
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "ClaiRISC_core"

#map options
set_option -frequency auto
set_option -run_prop_extract 0
set_option -fanout_limit 30
set_option -disable_io_insertion 0
set_option -verification_mode 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -fixgatedclocks 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/ClaiRISC_core.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -dup 0
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "rev_1"