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[/] [mesi_isc/] [trunk/] [syn/] [rpt/] [mesi_isc-Flow Summary.rpt] - Rev 4

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Flow Summary report for mesi_isc
Tue Nov  6 20:48:09 2012
Quartus II 32-bit Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Flow Summary                                                                       ;
+------------------------------------+-----------------------------------------------+
; Flow Status                        ; Successful - Tue Nov  6 14:54:24 2012         ;
; Quartus II 32-bit Version          ; 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition ;
; Revision Name                      ; mesi_isc                                      ;
; Top-level Entity Name              ; mesi_isc                                      ;
; Family                             ; Cyclone IV GX                                 ;
; Total logic elements               ; 72 / 29,440 ( < 1 % )                         ;
;     Total combinational functions  ; 72 / 29,440 ( < 1 % )                         ;
;     Dedicated logic registers      ; 45 / 29,440 ( < 1 % )                         ;
; Total registers                    ; 45                                            ;
; Total pins                         ; 190 / 307 ( 62 % )                            ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0 / 1,105,920 ( 0 % )                         ;
; Embedded Multiplier 9-bit elements ; 0 / 160 ( 0 % )                               ;
; Total GXB Receiver Channel PCS     ; 0 / 4 ( 0 % )                                 ;
; Total GXB Receiver Channel PMA     ; 0 / 4 ( 0 % )                                 ;
; Total GXB Transmitter Channel PCS  ; 0 / 4 ( 0 % )                                 ;
; Total GXB Transmitter Channel PMA  ; 0 / 4 ( 0 % )                                 ;
; Total PLLs                         ; 0 / 6 ( 0 % )                                 ;
; Device                             ; EP4CGX30CF23C6                                ;
; Timing Models                      ; Final                                         ;
+------------------------------------+-----------------------------------------------+


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