URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
[/] [minsoc/] [tags/] [release-0.9/] [utils/] [contributions/] [synthesis_makefile/] [Makefile] - Rev 42
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ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC
MINSOC = $(ROOT)/minsoc
MINSOC_RTL = $(MINSOC)/rtl/verilog
UART_RTL = $(ROOT)/uart16550/rtl/verilog
ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware
DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog
XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog
OR1200_RTL = $(ROOT)/or1200/rtl/verilog
help:
@echo " all: Synthesize and implement the SoC, then generate a bit stream"
@echo " soc: Synthesize the SoC"
@echo " translate: Convert the SoC's ngc file to an ngd file for mapping"
@echo " map: Express the SoC netlist in the target hardware"
@echo " par: Place the target hardware, then route the wires"
@echo " bitgen: Generate a programming file for the target FPGA"
@echo " clean: Delete all superfluous files generated by Xilinx tools"
@echo " distclean: Delete all generated files"
@echo " uart: Synthesize the UART"
@echo " debug: Synthesize the debug interface"
@echo " xilDebug: Synthesize the Xilinx JTAG user interface"
@echo " or1200: Synthesize the OR1200 processor"
all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit
soc: minsoc_top.ngc
translate: minsoc.ngd
map: minsoc.ncd
par: minsoc_par.ncd
bitgen: minsoc.bit
distclean:
rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log}
clean:
rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log}
minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc
xst -ifn "buildSupport/minsoc_top.xst"
rm -f minsoc_top_xst.xrpt
rm -f minsoc_top.srp
rm -f minsoc_top.lso
rm -rf _xmsgs
rm -rf xst
uart: uart_top.ngc
uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj
xst -ifn "buildSupport/uart_top.xst"
rm -f uart_top_xst.xrpt
rm -f uart_top.srp
rm -f uart_top.lso
rm -rf _xmsgs
rm -rf xst
debug: adbg_top.ngc
adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj
xst -ifn "buildSupport/adbg_top.xst"
rm -f adbg_top_xst.xrpt
rm -f adbg_top.srp
rm -f adbg_top.lso
rm -rf _xmsgs
rm -rf xst
xilDebug: xilinx_internal_jtag.ngc
xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj
xst -ifn "buildSupport/xilinx_internal_jtag.xst"
rm -f xilinx_internal_jtag_xst.xrpt
rm -f xilinx_internal_jtag.srp
rm -f xilinx_internal_jtag.lso
rm -rf _xmsgs
rm -rf xst
or1200: or1200_top.ngc
or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj
xst -ifn "buildSupport/or1200_top.xst"
rm -f or1200_top_xst.xrpt
rm -f or1200_top.srp
rm -f or1200_top.lso
rm -rf _xmsgs
rm -rf xst
minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc
ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd
rm -rf netlist.lst
rm -rf minsoc.bld
rm -rf minsoc*.xrpt
rm -rf xlnx_auto_0_xdb
rm -rf _xmsgs
minsoc.ncd : minsoc.ngd
map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
rm -rf minsoc.map
rm -rf minsoc.mrp
rm -rf minsoc.ngm
rm -rf minsoc.pcf
rm -rf minsoc.psr
rm -rf minsoc*.xml
rm -rf minsoc_top*.xrpt
rm -rf _xmsgs
minsoc_par.ncd: minsoc.ncd
par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd
rm -rf minsoc_par.pad
rm -rf minsoc_par.par
rm -rf minsoc_par.ptwx
rm -rf minsoc_par.unroutes
rm -rf minsoc_par.xpi
rm -rf minsoc_par_pad*
rm -rf minsoc_top*.xrpt
rm -rf _xmsgs
minsoc.bit: minsoc_par.ncd
bitgen -d -w minsoc_par.ncd minsoc.bit
rm -rf minsoc.bgn
rm -rf *.xwbt
rm -rf *.xml
rm -rf *.log
rm -rf _xmsgs