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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sim/] [results/] [wave.do.sav] - Rev 2

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[size] 1280 1001
[pos] -1 -1
*-29.000000 16828000000 285000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] minsoc_bench.
[treeopen] minsoc_bench.minsoc_top_0.
@28
minsoc_bench.reset
minsoc_bench.minsoc_top_0.or1200_top.iwb_cyc_o
minsoc_bench.minsoc_top_0.or1200_top.iwb_stb_o
minsoc_bench.minsoc_top_0.or1200_top.iwb_we_o
@22
minsoc_bench.minsoc_top_0.or1200_top.iwb_adr_o[31:0]
minsoc_bench.minsoc_top_0.or1200_top.iwb_dat_i[31:0]
@28
minsoc_bench.minsoc_top_0.or1200_top.iwb_ack_i
minsoc_bench.minsoc_top_0.or1200_top.dwb_cyc_o
minsoc_bench.minsoc_top_0.or1200_top.dwb_stb_o
minsoc_bench.minsoc_top_0.or1200_top.dwb_we_o
@22
minsoc_bench.minsoc_top_0.or1200_top.dwb_adr_o[31:0]
minsoc_bench.minsoc_top_0.or1200_top.dwb_dat_o[31:0]
@28
minsoc_bench.minsoc_top_0.or1200_top.dwb_ack_i
@22
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_sprs.sr[15:0]
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_dataa[31:0]
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_datab[31:0]
@28
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag_we
@22
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.result[31:0]
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.alu_op[3:0]
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_a[31:0]
minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_b[31:0]
@28
minsoc_bench.uart_stx
minsoc_bench.minsoc_top_0.uart_top.wb_cyc_i
minsoc_bench.minsoc_top_0.uart_top.wb_stb_i
minsoc_bench.minsoc_top_0.uart_top.wb_we_i
@22
minsoc_bench.minsoc_top_0.uart_top.wb_adr_i[4:0]
minsoc_bench.minsoc_top_0.uart_top.wb_dat8_i[7:0]
minsoc_bench.minsoc_top_0.uart_top.wb_dat8_o[7:0]
@28
minsoc_bench.minsoc_top_0.uart_top.wb_ack_o
minsoc_bench.minsoc_top_0.spi_flash_ss[1:0]
minsoc_bench.minsoc_top_0.spi_flash_sclk
minsoc_bench.minsoc_top_0.spi_flash_miso

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