Subversion Repositories mips_enhanced

##
###########################################################################
##  Copyright(C) 2006 by Xilinx, Inc. All rights reserved.               ##
##                                                                       ##
##  You may copy and modify these files for your own internal use solely ##
##  with Xilinx programmable logic devices and  Xilinx EDK system or     ##
##  create IP modules solely for Xilinx programmable logic devices and   ##
##  Xilinx EDK system. No rights are granted to distribute any files     ##
##  unless they are distributed in Xilinx programmable logic devices.    ##
##                                                                       ##
##  Source code is provided "as-is", with no obligation on the part of   ##
##  Xilinx to provide support.                                           ##
##                                                                       ##
###########################################################################
#
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# Target Board: Xilinx Spartan-3E 1600E Board Rev A                     ##
# Family: spartan3e                                                     ##
# Device: XC3S1600e                                                     ##
# Package: FG320                                                        ##
# Speed Grade: -4                                                       ##
##########################################################################
#

Net sys_clk_pin LOC=B8;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=K17;
Net sys_rst_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin PULLDOWN;

## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 14600 ps;
Net sys_rst_pin TIG;

NET "dlmb_port_BRAM_Clk" TNM_NET = "sys_clk_s";
NET "ddr_dev_clk_s" TNM_NET = "Device_Clk";

NET "fpga_0_DDR_CLK_FB" TNM_NET = "fpga_0_DDR_CLK_FB";
TIMESPEC "TS_fpga_0_DDR_CLK_FB" = PERIOD "fpga_0_DDR_CLK_FB" 7.2 ns HIGH 50 %;


NET "DBG_CLK_s" TNM_NET = "DBG_CLK_s";
TIMESPEC "TS_DBG_CLK_s" = PERIOD "DBG_CLK_s" 30 MHz HIGH 50 %;

TIMESPEC "TS_OPB_TO_DDR" = FROM "sys_clk_s" TO "Device_Clk"  TIG;
TIMESPEC "TS_DDR_TO_OPB" = FROM "Device_Clk" TO "sys_clk_s"  TIG;


## IO Devices constraints

#### Module RS232_DTE constraints

Net fpga_0_RS232_DTE_RX_pin LOC=U8;
Net fpga_0_RS232_DTE_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_DTE_TX_pin LOC=M13;
Net fpga_0_RS232_DTE_TX_pin IOSTANDARD = LVCMOS33;

#### Module FLASH_16Mx8 constraints

Net fpga_0_FLASH_16Mx8_Mem_A_pin<31> LOC=h17;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<31> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<30> LOC=j13;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<30> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<29> LOC=j12;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<28> LOC=j14;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<27> LOC=j15;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<26> LOC=j16;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<25> LOC=j17;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<24> LOC=k14;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<23> LOC=k15;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<22> LOC=k12;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<21> LOC=k13;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<20> LOC=l15;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<19> LOC=l16;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<18> LOC=t18;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<17> LOC=r18;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<16> LOC=t17;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<15> LOC=u18;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<14> LOC=t16;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<13> LOC=u15;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<12> LOC=v15;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<11> LOC=t12;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<10> LOC=v13;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<9> LOC=v12;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<8> LOC=n11;
Net fpga_0_FLASH_16Mx8_Mem_A_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7> LOC=n10;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6> LOC=p10;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5> LOC=r10;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4> LOC=v9;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3> LOC=u9;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2> LOC=r9;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1> LOC=m9;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0> LOC=n9;
Net fpga_0_FLASH_16Mx8_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_OEN_pin LOC=c18;
Net fpga_0_FLASH_16Mx8_Mem_OEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_WEN_pin LOC=d17;
Net fpga_0_FLASH_16Mx8_Mem_WEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> LOC=d16;
Net fpga_0_FLASH_16Mx8_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_16Mx8_emc_ben_gnd_pin LOC=c17;
Net fpga_0_FLASH_16Mx8_emc_ben_gnd_pin IOSTANDARD = LVCMOS33;

#### Module DDR_SDRAM_32Mx16 constraints

Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin LOC=J5;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin LOC=J4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> LOC=P2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> LOC=N5;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> LOC=T2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> LOC=N4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> LOC=H2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> LOC=H1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> LOC=H3;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> LOC=H4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> LOC=E4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> LOC=P1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> LOC=R2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> LOC=R3;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> LOC=T1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> LOC=K6;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> LOC=K5;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin LOC=C2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin LOC=K3;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin LOC=K4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin LOC=C1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin LOC=D1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> LOC=J1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> LOC=J2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> LOC=G3;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> LOC=L6;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> LOC=H5;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> LOC=H6;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> LOC=G5;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> LOC=G6;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> LOC=F2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> LOC=F1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> LOC=E1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> LOC=E2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> LOC=M6;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> LOC=M5;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> LOC=M4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> LOC=M3;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> LOC=L4;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> LOC=L3;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> LOC=L1;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> PULLUP;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> LOC=L2;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> PULLUP;

#### Module Ethernet_MAC constraints

Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=T7;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=V3;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=U13;
Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=V2;
Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=V8;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=T11;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=U11;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=V14;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=U6;
Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U14;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=P16;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=R11;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T15;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=R5;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=T5;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_Mii_clk_pin LOC=P9;
Net fpga_0_Ethernet_MAC_PHY_Mii_clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_Ethernet_MAC_PHY_Mii_data_pin LOC=U5;
Net fpga_0_Ethernet_MAC_PHY_Mii_data_pin IOSTANDARD = LVCMOS33;

Net fpga_0_DDR_CLK_FB LOC=B9;
Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS33;

Net SPI_ROM_CS_pin LOC=U3 | PULLUP;  ## This is to force the SPI ROM to not be selected(drive high)
Net SPI_ROM_CS_pin IOSTANDARD = LVCMOS33;