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# Synplicity, Inc. constraint file
# Z:\LEON3SDE\ALTERA\grlib-eval-1.0.8-ge\boards\ge-hpe-mini-lattice2\default.sdc
# Written on Wed Aug 16 13:55:14 2006
# by Synplify Pro, Synplify Pro 8.6.1 Scope Editor

#
# Collections
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#
# Clocks
#
define_clock            -name {clkgen0.clkm_inferred_clock}  -freq 60.000 -clockgroup clkmgroup
define_clock            -name {clkgen0.ddrclk0_inferred_clock}  -freq 120.000 -clockgroup ddrclkgroup

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# Clock to Clock
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# Inputs/Outputs
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define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
define_input_delay               -default  4.00 -improve 0.00 -route 0.00 -ref {clkgen0.ddrclk0_inferred_clock:r}

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# Registers
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# Multicycle Path
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# False Path
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# Path Delay
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# Attributes
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define_global_attribute          syn_useioff {1}
define_global_attribute          syn_netlist_hierarchy {1}

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# I/O standards
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# Other Constraints
#