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# Synplicity, Inc. constraint file
# /home/jiri/ibm/vhdl/grlib/boards/gr-pci-xc2v/default.sdc
# Written on Thu May  3 12:48:24 2007
# by Synplify Pro, Synplify Pro 8.6.2U Scope Editor

#
# Collections
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# Clocks
#
define_clock -disable   -name {clk}  -freq 50.000 -clockgroup default_clkgroup -route 5.000
define_clock            -name {pci_clk}  -period 30.000 -clockgroup pci_clkgroup -route 5.000

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# Clock to Clock
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# Inputs/Outputs
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define_output_delay -disable     -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
define_input_delay -disable      -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
define_output_delay              -default  19.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
define_input_delay               -default  23.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
define_input_delay               {pci_rst}  0.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}

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# Registers
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# Multicycle Path
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# False Path
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# Path Delay
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# Attributes
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define_global_attribute          syn_useioff {1}
define_global_attribute -disable syn_netlist_hierarchy {0}

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# I/O standards
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# Compile Points
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# Other Constraints
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