Subversion Repositories mips_enhanced

LIST FileManager
VALUE "<project>/../../lib/grlib/stdlib/version.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/stdlib/stdlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/stdlib/stdio.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/util/util.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/sparc/sparc.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/sparc/sparc_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/sparc/cpu_disas.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/modgen/multlib.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/modgen/leaves.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/amba.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/devices.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/defmst.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/apbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/ahbctrl.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/dma2ahb_pkg.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/dma2ahb.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
STATE="utd"
LIBRARY="grlib"
ENDFILE
VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
STATE="utd"
LIBRARY="synplify"
ENDFILE
VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/allpads.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/alltap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkgen.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkmux.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkand.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ddr_ireg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ddr_oreg.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ddrphy.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram64.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram_2p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncram_dp.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/syncfifo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/regfile_3p.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/tap.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/techbuf.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/clkpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/inpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/inpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iodpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iopad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/iopad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/lvds_combo.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/odpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/outpad_ds.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/toutpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/skew_outpad.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grspwc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grlfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grfpw_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/mul_61x61.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/cpu_disas_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/grusbhc_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ringosc.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/techmap/maps/ssrctrl_net.vhd,hdl"
STATE="utd"
LIBRARY="techmap"
ENDFILE
VALUE "<project>/../../lib/spw/comp/spwcomp.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../../lib/spw/wrapper/grspw_gen.vhd,hdl"
STATE="utd"
LIBRARY="spw"
ENDFILE
VALUE "<project>/../../lib/eth/comp/ethcomp.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/greth_pkg.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/eth_rstgen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/eth_ahb_mst.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/greth_tx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/greth_rx.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/core/grethc.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/wrapper/greth_gen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/eth/wrapper/greth_gbit_gen.vhd,hdl"
STATE="utd"
LIBRARY="eth"
ENDFILE
VALUE "<project>/../../lib/opencores/occomp/occomp.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/can/cancomp.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/can/can_top.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/can/can_top_core_sync.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/i2c/i2c_master_bit_ctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/i2c/i2c_master_byte_ctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/i2c/i2coc.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/spi/simple_spi_top.v,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ud_cnt.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ro_cnt.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_dma_fifo.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_dma_actrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_dma_tctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_pio_tctrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_pio_actrl.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_controller.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/atahost_pio_controller.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ocidec2_controller.vhd,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ata/ata_device_oc.v,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/opencores/ac97/ac97_top.v,hdl"
STATE="utd"
LIBRARY="opencores"
ENDFILE
VALUE "<project>/../../lib/gaisler/arith/arith.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/arith/mul32.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/arith/div32.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/memctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/sdctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/sdmctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/srctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/memctrl/spimctrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/leon3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/reg_zero.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmuconfig.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmuiface.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libmmu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libiu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/libproc3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/cachemem.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_icache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_dcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_acache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmutlbcam.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmulrue.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmulru.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmutlb.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmutw.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mmu_cache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/acache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/dcache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/icache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/cache.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/cpu_disasx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/grfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/mfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/grlfpwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/tbufmem.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/dsu3x.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/dsu3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/proc3.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/leon3s.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/leon3cg.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/irqmp.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/grfpwxsh.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/grfpushwx.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/leon3sh.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/my_mux.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/leon3/top.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/can/can.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/can/can_mod.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/can/can_oc.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/can/can_mc.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/can/canmux.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/can/can_rd.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/misc.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/rstgen.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/gptimer.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/ahbram.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/ahbtrace.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/ahbmst.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/grgpio.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/ahbstat.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/logan.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/apbps2.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/charrom_package.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/charrom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/apbvga.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/ahbdma.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/svgactrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/i2cmst.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/spictrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/i2cslv.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/wild.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/misc/wild2ahb.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/net/net.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/uart/uart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/uart/libdcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/uart/apbuart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/uart/dcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/uart/dcom_uart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/uart/ahbuart.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/i2c_slave_model.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/sim.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/sram.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/ata_device.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/sram16.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/phy.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/sim/ahbrep.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/jtag/jtag.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/jtag/libjtagcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/jtag/jtagcom.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/jtag/ahbjtag.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/jtag/ahbjtag_bsd.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/jtag/jtagtst.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/greth/ethernet_mac.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/greth/greth.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/greth/greth_gbit.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/greth/grethm.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/spacewire/spacewire.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/spacewire/grspw.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/spacewire/grspw2.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/spacewire/grspwm.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/usb/grusb.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/ata.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/ata_inf.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/atahost_amba_slave.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/atahost_ahbmst.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/ocidec2_amba_slave.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/atactrl_nodma.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/atactrl_dma.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/ata/atactrl.vhd,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/decode_pipe1.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/EXEC_stage.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/ulit.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/ctl_fsm1.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/RF_stage1.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/RF_components1.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/forward.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/mips789_defs.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/hazard_unit.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/forward.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/gaisler/vlog/core1.v,hdl"
STATE="utd"
LIBRARY="gaisler"
ENDFILE
VALUE "<project>/../../lib/esa/memoryctrl/memoryctrl.vhd,hdl"
STATE="utd"
LIBRARY="esa"
ENDFILE
VALUE "<project>/../../lib/esa/memoryctrl/mctrl.vhd,hdl"
STATE="utd"
LIBRARY="esa"
ENDFILE
VALUE "<project>/../../lib/micron/sdram/mobile_sdr.v,hdl"
STATE="utd"
LIBRARY="micron"
ENDFILE
VALUE "<project>/../../lib/micron/sdram/components.vhd,hdl"
STATE="utd"
LIBRARY="micron"
ENDFILE
VALUE "<project>/../../lib/micron/sdram/mt48lc16m16a2.vhd,hdl"
STATE="utd"
LIBRARY="micron"
ENDFILE
VALUE "<project>/../../lib/work/debug/debug.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/../../lib/work/debug/grtestmod.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/../../lib/work/debug/cpu_disas.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/config.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/ahbrom.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/vga_clkgen.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/leon3mp.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE
VALUE "<project>/testbench.vhd,hdl"
STATE="utd"
LIBRARY="work"
ENDFILE