URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [forward_node/] [_primary.vhd] - Rev 2
Compare with Previous | Blame | View Log
library verilog; use verilog.vl_types.all; entity forward_node is port( rn : in vl_logic_vector(4 downto 0); alu_wr_rn : in vl_logic_vector(4 downto 0); alu_we : in vl_logic; mem_wr_rn : in vl_logic_vector(4 downto 0); mem_we : in vl_logic; mux_fw : out vl_logic_vector(2 downto 0) ); end forward_node;