URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [xst/] [work/] [hdllib.ref] - Rev 2
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MO shifter_ff NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg40/shifter__ff.bin 1275653620MO hazard_unit NULL ../../lib/gaisler/vlog/hazard_unit.v vlg39/hazard__unit.bin 1275653620MO muldiv NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg39/muldiv.bin 1275653620MO ctl_FSM NULL ../../lib/gaisler/vlog/ctl_fsm1.v vlg50/ctl___f_s_m.bin 1275653620MO cal_cpi NULL ../../lib/gaisler/vlog/ulit.v vlg63/cal__cpi.bin 1275653619MO ext_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg28/ext__ctl__reg__clr.bin 1275653620MO cmp_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg7F/cmp__ctl__reg.bin 1275653620MO ext_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg29/ext__ctl__reg__cls.bin 1275653620EN ahbrom NULL C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/ahbrom.vhd sub00/vhpl01 1275653968MO spc_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg3F/spc__reg__clr.bin 1275653620MO spc_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg40/spc__reg__cls.bin 1275653620MO alu_we_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg6F/alu__we__reg__clr__cls.bin 1275653619MO muxa_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg3E/muxa__ctl__reg__clr.bin 1275653620MO ext_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg4C/ext__ctl__reg.bin 1275653620MO muxa_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg3F/muxa__ctl__reg__cls.bin 1275653620MO forward_node NULL ../../lib/gaisler/vlog/forward.v vlg2E/forward__node.bin 1275653620MO muxb_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg3C/muxb__ctl__reg__clr__cls.bin 1275653619MO dmem_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg7B/dmem__ctl__reg__clr__cls.bin 1275653619MO pc_gen NULL ../../lib/gaisler/vlog/RF_components1.v vlg3C/pc__gen.bin 1275653620PH config NULL C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/config.vhd sub00/vhpl00 1275653967MO r5_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg5D/r5__reg__clr__cls.bin 1275653620MO r2_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg6A/r2__reg__clr__cls.bin 1275653620MO wb_mux_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg0A/wb__mux__ctl__reg__clr__cls.bin 1275653619MO alu_func_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg56/alu__func__reg__clr.bin 1275653620MO alu_func_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg57/alu__func__reg__cls.bin 1275653620AR ahbrom rtl C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/ahbrom.vhd sub00/vhpl02 1275653969MO r32_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg01/r32__reg__clr__cls.bin 1275653620MO r2_reg NULL ../../lib/gaisler/vlog/ulit.v vlg11/r2__reg.bin 1275653620MO alu_func_reg NULL ../../lib/gaisler/vlog/ulit.v vlg5A/alu__func__reg.bin 1275653620MO r4_rdaddr_reg NULL ../../lib/gaisler/vlog/ulit.v vlg37/r4__rdaddr__reg.bin 1275653620MO or32 NULL ../../lib/gaisler/vlog/ulit.v vlg06/or32.bin 1275653619MO cmp_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg2B/cmp__ctl__reg__clr.bin 1275653620MO r4_asi_reg NULL ../../lib/gaisler/vlog/ulit.v vlg57/r4__asi__reg.bin 1275653620MO cmp_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg2C/cmp__ctl__reg__cls.bin 1275653620MO shifter_tak NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg70/shifter__tak.bin 1275653620MO rd_sel NULL ../../lib/gaisler/vlog/ulit.v vlg41/rd__sel.bin 1275653619MO mips_core NULL ../../lib/gaisler/vlog/core1.v vlg3D/mips__core.bin 1275653620MO forward NULL ../../lib/gaisler/vlog/forward.v vlg15/forward.bin 1275653620MO jack NULL ../../lib/gaisler/vlog/ulit.v vlg15/jack.bin 1275653619MO fsm_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg25/fsm__ctl__reg.bin 1275653620MO pc_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg64/pc__reg__clr.bin 1275653620MO pc_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg65/pc__reg__cls.bin 1275653620EN vga_clkgen NULL C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd sub00/vhpl03 1275653970MO rd_sel_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg52/rd__sel__reg__clr.bin 1275653620MO rd_sel_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg4F/rd__sel__reg__clr__cls.bin 1275653619MO rd_sel_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg53/rd__sel__reg__cls.bin 1275653620MO muxb_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg0F/muxb__ctl__reg__clr.bin 1275653620MO r32_reg NULL ../../lib/gaisler/vlog/ulit.v vlg08/r32__reg.bin 1275653620MO muxb_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg10/muxb__ctl__reg__cls.bin 1275653620MO add32 NULL ../../lib/gaisler/vlog/ulit.v vlg1A/add32.bin 1275653619MO muldiv_ff NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg00/muldiv__ff.bin 1275653620MO fw_latch1 NULL ../../lib/gaisler/vlog/forward.v vlg1D/fw__latch1.bin 1275653620MO mips_alu NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg3A/mips__alu.bin 1275653620MO fw_latch5 NULL ../../lib/gaisler/vlog/forward.v vlg21/fw__latch5.bin 1275653620MO fsm_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg7E/fsm__ctl__reg__clr__cls.bin 1275653619MO r3_reg NULL ../../lib/gaisler/vlog/ulit.v vlg02/r3__reg.bin 1275653620MO pipelinedregs NULL ../../lib/gaisler/vlog/decode_pipe1.v vlg27/pipelinedregs.bin 1275653620MO wb_mux NULL ../../lib/gaisler/vlog/ulit.v vlg2E/wb__mux.bin 1275653619MO alu_we_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg72/alu__we__reg__clr.bin 1275653620MO alu_we_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg73/alu__we__reg__cls.bin 1275653620MO ins_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg38/ins__reg__clr__cls.bin 1275653619MO r3_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg3B/r3__reg__clr__cls.bin 1275653620MO pc_gen_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg7F/pc__gen__ctl__reg.bin 1275653620MO muxb_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg23/muxb__ctl__reg.bin 1275653620MO pc_reg NULL ../../lib/gaisler/vlog/ulit.v vlg48/pc__reg.bin 1275653620MO muxa_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg42/muxa__ctl__reg.bin 1275653620MO wb_we_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg11/wb__we__reg__clr.bin 1275653620MO wb_we_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg12/wb__we__reg__cls.bin 1275653620MO spc_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg6C/spc__reg__clr__cls.bin 1275653620MO wb_we_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg1E/wb__we__reg__clr__cls.bin 1275653619MO ins_reg NULL ../../lib/gaisler/vlog/ulit.v vlg1F/ins__reg.bin 1275653620EN leon3mp NULL C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/leon3mp.vhd sub00/vhpl05 1275653972MO wb_mux_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg3D/wb__mux__ctl__reg__clr.bin 1275653620MO dmem_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg42/dmem__ctl__reg.bin 1275653620MO wb_mux_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg3E/wb__mux__ctl__reg__cls.bin 1275653620AR vga_clkgen struct C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd sub00/vhpl04 1275653971MO pc_gen_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg2B/pc__gen__ctl__reg__clr.bin 1275653620MO alu_we_reg NULL ../../lib/gaisler/vlog/ulit.v vlg36/alu__we__reg.bin 1275653620MO r5_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg40/r5__reg__clr.bin 1275653620MO pc_gen_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg2C/pc__gen__ctl__reg__cls.bin 1275653620MO r5_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg41/r5__reg__cls.bin 1275653620MO rf_stage NULL ../../lib/gaisler/vlog/RF_stage1.v vlg13/rf__stage.bin 1275653620MO r32_inst_reg NULL ../../lib/gaisler/vlog/ulit.v vlg79/r32__inst__reg.bin 1275653620MO r4_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg5F/r4__reg__clr.bin 1275653620MO r4_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg60/r4__reg__cls.bin 1275653620MO r32_pc_reg NULL ../../lib/gaisler/vlog/ulit.v vlg36/r32__pc__reg.bin 1275653620MO r4_reg NULL ../../lib/gaisler/vlog/ulit.v vlg73/r4__reg.bin 1275653620MO fsm_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg71/fsm__ctl__reg__clr.bin 1275653620MO r3_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg7E/r3__reg__clr.bin 1275653620MO fsm_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg72/fsm__ctl__reg__cls.bin 1275653620MO r3_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg7F/r3__reg__cls.bin 1275653620MO fwd_mux NULL ../../lib/gaisler/vlog/forward.v vlg26/fwd__mux.bin 1275653620AR leon3mp rtl C:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/leon3mp.vhd sub00/vhpl06 1275653973MO reg_array NULL ../../lib/gaisler/vlog/RF_components1.v vlg38/reg__array.bin 1275653620MO compare NULL ../../lib/gaisler/vlog/RF_components1.v vlg5B/compare.bin 1275653620MO spc_reg NULL ../../lib/gaisler/vlog/ulit.v vlg53/spc__reg.bin 1275653620MO r2_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg1D/r2__reg__clr.bin 1275653620MO r2_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg1E/r2__reg__cls.bin 1275653620MO wb_we_reg NULL ../../lib/gaisler/vlog/ulit.v vlg45/wb__we__reg.bin 1275653620MO branch_reg_whold NULL ../../lib/gaisler/vlog/ulit.v vlg7C/branch__reg__whold.bin 1275653620MO r1_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg3C/r1__reg__clr.bin 1275653620MO rd_sel_reg NULL ../../lib/gaisler/vlog/ulit.v vlg16/rd__sel__reg.bin 1275653620MO ext NULL ../../lib/gaisler/vlog/RF_components1.v vlg29/ext.bin 1275653620MO r1_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg3D/r1__reg__cls.bin 1275653620MO exec_stage NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg00/exec__stage.bin 1275653620MO r32_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg24/r32__reg__clr.bin 1275653620MO r32_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg25/r32__reg__cls.bin 1275653620MO r4_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg0C/r4__reg__clr__cls.bin 1275653620MO r1_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg19/r1__reg__clr__cls.bin 1275653620MO decode_pipe NULL ../../lib/gaisler/vlog/decode_pipe1.v vlg05/decode__pipe.bin 1275653620MO alu_muxa NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg60/alu__muxa.bin 1275653620MO alu_muxb NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg61/alu__muxb.bin 1275653620MO decoder NULL ../../lib/gaisler/vlog/decode_pipe1.v vlg02/decoder.bin 1275653620MO ext_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg45/ext__ctl__reg__clr__cls.bin 1275653619MO r32_data_reg NULL ../../lib/gaisler/vlog/ulit.v vlg75/r32__data__reg.bin 1275653620MO ins_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg4B/ins__reg__clr.bin 1275653620MO ins_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg4C/ins__reg__cls.bin 1275653620MO pc_gen_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg18/pc__gen__ctl__reg__clr__cls.bin 1275653619MO cmp_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg18/cmp__ctl__reg__clr__cls.bin 1275653619MO r5_reg NULL ../../lib/gaisler/vlog/ulit.v vlg64/r5__reg.bin 1275653620MO dmem_ctl_reg_clr NULL ../../lib/gaisler/vlog/ulit.v vlg3E/dmem__ctl__reg__clr.bin 1275653620MO alu_func_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg13/alu__func__reg__clr__cls.bin 1275653619MO dmem_ctl_reg_cls NULL ../../lib/gaisler/vlog/ulit.v vlg3F/dmem__ctl__reg__cls.bin 1275653620MO wb_mux_ctl_reg NULL ../../lib/gaisler/vlog/ulit.v vlg31/wb__mux__ctl__reg.bin 1275653620MO alu NULL ../../lib/gaisler/vlog/EXEC_stage.v vlg0A/alu.bin 1275653620MO pc_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg41/pc__reg__clr__cls.bin 1275653620MO r1_reg NULL ../../lib/gaisler/vlog/ulit.v vlg20/r1__reg.bin 1275653620MO muxa_ctl_reg_clr_cls NULL ../../lib/gaisler/vlog/ulit.v vlg7B/muxa__ctl__reg__clr__cls.bin 1275653619