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<h3><span style="font-family: helvetica,arial,sans-serif;">LEON3MP - a
reference LEON3 design with MP support<br>
</span></h3>
<h4 style="font-family: helvetica,arial,sans-serif;">Introduction</h4>
<small><span style="font-family: helvetica,arial,sans-serif;">The
LEON3MP provides a reference
design for LEON3-based systems. LEON3MP is highly configurable, and
consists of the following IP cores:<br>
</span></small>
<ul>
<li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
4 LEON3 processor
cores with MP support</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
debug support unit (DSU) for LEON3<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit PROM/SRAM
controller</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">8-/16-/32-/64-bit
PROM/SRAM/SDRAM controller</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit
PCI interface, target-only
or initiator/target with
FIFO and DMA</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Round-robin
AHB arbiter and controller with plug&play support</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">AHB/APB bridge with
plug&play support<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
interrupt controller</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit modular timer
unit</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
2 UARTs with FIFO<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">10/100 ethernet MAC</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">CAN interface<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
communication link</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Etherner debug
communication link</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug link<br>
</span></small></li>
</ul>
<small><span style="font-family: helvetica,arial,sans-serif;">
<br>
The LEON3 MP design is provided together with GRLIB, and is
located in grlib/designs/leon3mp.<br>
<br>
</span></small>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">LEON3MP
Block diagram</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;"><img alt="" src="../../doc/grip/leon3mp.gif" height="393" width="615"><br>
</span></small>
<h4><span style="font-family: helvetica,arial,sans-serif;">Reference
architecture</span></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">The
LEON3MP is made up by cores from the GRLIB IP library, which are
connected together via the AMBA AHB and APB buses. The plug&play
configuration method of GRLIB makes it possible to assign any
combination of addresses and interrupts to the cores. However, to be
software compatible with simple operating systems such as the LEON
Bare-C cross-compiler, some of the vital cores must be assigned to
predefined addresses and interrupts. The table below shows the
reference assigment in the LEON3MP design:<br>
<br>
</span></small>
<table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
<tbody>
<tr>
<th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory controller<br>
(separate SRAM and SDRAM controllers, or
combined LEON2 controller)<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x00000000 -
0x20000000 : PROM<br>
0x20000000 - 0x40000000 : external I/O bus<br>
0x40000000 - 0x80000000 : SRAM/SDRAM<br>
0x80000000 - 0x80000100 : Memory controller registers (APB)<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">APB bridge<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000000 -
0x80100000 : APB bus<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000100 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 : UART
registers</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">2</span></small><br>
</td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt controller</span></small><br>
</td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300 : IRQ
registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Timer unit<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0x80000400 : timer
registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">8, 9<br>
</span></small></td>
</tr>
<tr>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">LEON3 debug support
unit (DSU)<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x90000000 -
0xA0000000 : DSU registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
</tbody>
</table>
<small><span style="font-family: helvetica,arial,sans-serif;"><br>
Additional (optional) IP cores are assigned addresses and interrupts as
desribed in the table below. These assignments are LEON3MP specific and
can be changed without impact on software compatibility.<br>
<br>
</span></small>
<table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
<tbody>
<tr>
<th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">PCI initiator/target interface<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: courier new,courier,monospace;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xE0000000 -
0xF0000000 : PCI initiator access <br>
0xFFF80000 - 0xFFFA0000 : PCI special cycles<br>
0x80000400 - 0x80000500 : PCI registers<br>
0x80000600 - 0x80000700 : PCI DMA registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">PCI arbiter</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000A00 -
0x80000B00 : PCI arbiter registers</span></small></td>
<td valign="top"><br>
</td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">PCI trace buffer<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80010000 -
0x80020000 : PCI trace buffer registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
communication link<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000700 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000800 : AHB UART
registers</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Ethernet debug
communication link</span></small><br>
</td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug
communication link</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">10/100 Mbit ethernet MAC<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xFFFB0000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xFFFB1000 :
ethernet
control registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">12</span></small></td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">CAN interface</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xFFFC0000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xFFFC1000 : CAN
control registers</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">13</span></small></td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">On-chip RAM<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xA0000000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xA0100000 : On-chip
RAM<br>
</span></small></td>
<td valign="top"><br>
</td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000900 -
0x80000A00 : Secondary UART<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">3</span></small></td>
</tr>
</tbody>
</table>
<br>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">
</span></small></h4>
<h4><span style="font-family: helvetica,arial,sans-serif;">Configuration</span></h4>
<div style="text-align: left;"><small><span style="font-family: helvetica,arial,sans-serif;">The configuartion of
the LEON3MP design is defined through the config package located <a href="config.vhd">config.vhd</a>.
This file can be automatically generated using a GUI based on tkconfig.
To launch the GUI, do 'make xconfig'. After the configuration is
completed, save and
exit the tool and config.vhd will be created automatically.
<br>
<br>
Alternatively, a pre-defined configuration can be installed for two
specific FPGA boards: gr-pci-xc2v and gr-cpci-xc2v. In
this case, set
the BOARD variable in the local <a href="Makefile">Makefile</a> to the
desired board type, and issue the command
'make config' to generate the configuration file.<br>
<br>
<img alt="" src="../share/gui.gif" height="148" width="561"><br>
<br>
<i>Figure 1. LEON3MP configuration GUI</i><br style="font-family: helvetica,arial,sans-serif;">
</span></small><small>
</small></div>
<h4><span style="font-family: helvetica,arial,sans-serif;">Simulation</span></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
simulate the testbench, first compile the model for simulation. This
can be done automatically for three different simulators. Execute one
of the following commands:</span><br style="font-family: helvetica,arial,sans-serif;">
</small>
<ul style="font-family: helvetica,arial,sans-serif;">
<li><small>make vsim</small></li>
<li><small>make ncsim</small></li>
<li><small>make ghdl</small></li>
</ul>
<small><span style="font-family: helvetica,arial,sans-serif;">For vsim,
start the simulation with 'vsim testbench' and do 'run 100'. This
should print the current LEON3MP configuration:</span><br style="font-family: helvetica,arial,sans-serif;">
</small><br>
<small><span style="font-family: courier new,courier,monospace;">$ vsim
-c -quiet testbench</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Reading
/usr/local/model58/tcl/vsim/pref.tcl</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Reading
/home/jiri/modelsim.tcl</span><br style="font-family: courier new,courier,monospace;">
</small><small><span style="font-family: courier new,courier,monospace;"></span></small><br style="font-family: courier new,courier,monospace;">
<small><span style="font-family: courier new,courier,monospace;"># 5.8</span><br style="font-family: courier new,courier,monospace;">
</small><small><span style="font-family: courier new,courier,monospace;"></span><big><tt>#
VSIM 1> run<br>
# LEON3 Demonstration design<br>
# GRLIB Version 0.13<br>
# Target technology: virtex2 , memory library: virtex2<br>
# ahbctrl: mst0: Gaisler
Research Leon3 SPARC V8
Processor<br>
# ahbctrl: mst1: Gaisler
Research AHB Debug UART<br>
# ahbctrl: mst2: Gaisler
Research Fast 32-bit PCI
Bridge<br>
# ahbctrl: mst3: Gaisler
Research AMBA DMA controller<br>
# ahbctrl: mst5: Gaisler
Research OC ethernet AHB
interface<br>
# ahbctrl: slv0: Gaisler
Research Simple SRAM
Controller<br>
# ahbctrl: memory at 0x00000000,
size 16 Mbyte, cacheable, prefetch<br>
# ahbctrl: memory at 0x40000000,
size 16 Mbyte, cacheable, prefetch<br>
# ahbctrl: slv1: Gaisler
Research AHB/APB Bridge<br>
# ahbctrl: memory at 0x80000000,
size 1 Mbyte<br>
# ahbctrl: slv2: Gaisler
Research Leon3 Debug Support
Unit<br>
# ahbctrl: memory at 0x90000000,
size 256 Mbyte<br>
# ahbctrl: slv4: Gaisler
Research Fast 32-bit PCI
Bridge<br>
# ahbctrl: memory at 0xe0000000,
size 256 Mbyte<br>
# ahbctrl: I/O port at 0xfff80000,
size 128kbyte<br>
# ahbctrl: slv5: Gaisler
Research OC ethernet AHB
interface<br>
# ahbctrl: I/O port at 0xfffb0000,
size 4kbyte<br>
# ahbctrl: slv6: Gaisler
Research OC CAN AHB interface<br>
# ahbctrl: I/O port at 0xfffc0000,
size 4kbyte<br>
# ahbctrl: slv7: Gaisler
Research Generic AHB SRAM
module<br>
# ahbctrl: memory at 0xa0000000,
size 1 Mbyte, cacheable, prefetch<br>
# ahbctrl: AHB arbiter/multiplexer rev 1<br>
# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte<br>
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte<br>
# apbctrl: APB Bridge at 0x80000000 rev 1<br>
# apbctrl: slv1: Gaisler
Research Generic UART<br>
# apbctrl: I/O ports at 0x80000100,
size 256 byte<br>
# apbctrl: slv2: Gaisler
Research Multi-processor
Interrupt Ctrl.<br>
# apbctrl: I/O ports at 0x80000200,
size 256 byte<br>
# apbctrl: slv3: Gaisler
Research Modular Timer Unit<br>
# apbctrl: I/O ports at 0x80000300,
size 256 byte<br>
# apbctrl: slv4: Gaisler
Research Fast 32-bit PCI
Bridge<br>
# apbctrl: I/O ports at 0x80000400,
size 256 byte<br>
# apbctrl: slv5: Gaisler
Research AMBA DMA controller<br>
# apbctrl: I/O ports at 0x80000500,
size 256 byte<br>
# apbctrl: slv7: Gaisler
Research AHB Debug UART<br>
# apbctrl: I/O ports at 0x80000700,
size 256 byte<br>
# ahbram7: AHB SRAM Module rev 1, 2 kbytes<br>
# can_oc6: Opencores CAN MAC, rev 0, irq 13<br>
# eth_oc5: Wishbone/AHB interface for OC ethernet MAC, irq 12<br>
# eth_oc5: Opencores 10/100 Mbit ethernet MAC, rev 0<br>
# pci_mtf4: 32-bit PCI/AHB bridge rev 0, 2 Mbyte PCI memory BAR,
8-word FIFOs<br>
# dmactrl5: 32-bit DMA controller & AHB/AHB bridge rev 0<br>
# gptimer3: GR Timer Unit rev 0, 16-bit scaler, 1 32-bit timers, irq 8<br>
# irqmp: Multi-processor Interrupt Controller rev 1, #cpu 1<br>
# apbuart1: Generic UART rev 1, irq 2<br>
# srctrl0: 32-bit PROM/SRAM controller rev 0<br>
# ahbuart7: AHB Debug UART rev 0<br>
# dsu3_2: LEON3 Debug support unit<br>
# leon3_0: LEON3 SPARC V8 processor rev 0<br>
# leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte</tt></big><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"></span><span style="font-family: courier new,courier,monospace;"></span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">VSIM 2>
run -all<br>
#<br># **** GRLIB system test starting ****<br>
# Leon3 SPARC V8 Processor<br>
# register file<br>
# multiplier<br>
# radix-2 divider<br>
# cache system<br>
# Multi-processor Interrupt Ctrl.<br>
# Generic UART<br>
# Modular Timer Unit<br>
# Test passed, halting with IU error mode<br>
#<br>
# ** Failure: *** IU in error mode, simulation halted ***<br>
# Time: 669213500 ps Iteration: 1 Process: /testbench/iuerr File: testbench.vhd<br>
# Break at testbench.vhd line 263<br>
# Stopped at testbench.vhd line 263<br>
<br>
</span></small><h4><small><span style="font-family: helvetica,arial,sans-serif;">Synthesis<br>
</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
synthesize and perform place&route for any of the supported
FPGA boards, set the BOARD variable in the Makefile and issue the
appropriate make commands for your tool chain (see GRLIB User's Manual
for details). Alternatively, the design can be implemented using
the graphical XGrlib tool, which is started with 'make xgrlib'.<br>
<br>
<br>
<img alt="" src="../../doc/grlib/xgrlib.gif" height="537" width="619"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> </span></small><br>
<div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></div>
<small><span style="font-family: helvetica,arial,sans-serif;">
<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><i>Figure 2. XGrlib
implementation tool</i></span></small><br>
<small><span style="font-family: helvetica,arial,sans-serif;"><br>
<br>
For ASIC synthesis, scripts to synthesise LEON3MP towards the Atmel
ATC18 technology are provided. Run either atc18.dc or atc18.rc to
synthesise with Synopsys DC, or Cadence RC.<br>
<br>
</span></small>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">Software
development</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<ul>
<li><small><span style="font-family: helvetica,arial,sans-serif;"><b><a href="http://www.rtems.org/">RTEMS</a>:</b> to
develop RTEMS applications, download and install the <a href="http://www.gaisler.com/products/rcc.html">LEON3 RTEMS
Cross-compiler</a> from gaisler.com. The LEON3 bsp automatically
detects
the location of UARTs, timers, interrupt controller and ethernet core
using the plug&play information. Full sources of kernel, libraries and tools available.</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;"><b>Bare-C</b>: a <a href="http://www.gaisler.com/doc/bcc.html">LEON3 bare-C compiler</a>
is available for download from gaisler.com. Come with full source code for both the
low-level I/O routines as well as the mkprom prom builder.</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;"><a href="http://sourceware.org/ecos/"><b>eCos</b></a>: a Leon3 port supporting FPU, SMP and single-vector trapping is available for ecos-current. Use Bare-C compiler to build.<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;"><b>Linux</b>: a Leon3 port of uClinux and linux-2.6.11 is available in the <a href="http://www.gaisler.com/products/linux.html">snapgear
linux distribution</a>.</span></small></li>
</ul>
<small><span style="font-family: helvetica,arial,sans-serif;"></span></small>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">Debugging<br>
</span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">The
on-chip debug support unit (DSU) makes debugging of target hardware
relatively easy. Both JTAG, serial (RS232) and ethernet-based debug links are
available, and can be used </span></small><small><span style="font-family: helvetica,arial,sans-serif;">download and debug
code. Debugging is controlled through the <a href="http://www.gaisler.com/products/grmon/grmon.html">GRMON debug
monitor</a>.</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> A sample GRMON
session looks like this:<br>
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">$ grmon
-grlib -i -u</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> GRMON -
The LEON multi purpose monitor v1.0.6</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Copyright
(C) 2004, Gaisler Research - all rights reserved.</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> For
latest updates, go to http://www.gaisler.com/</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Comments
or bug-reports to grmon@gaisler.com</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> GRLIB
DSU Monitor backend 1.0.1 (professional version)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> using
port /dev/ttyS0 @ 115200 baud</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> initialising
...........</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Component
Vendor</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Leon3
SPARC V8
Processor
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> AHB
Debug
UART
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Simple
32-bit PCI
Target
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> 10/100
Mbit Ethernet
MAC
Opencores</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> LEON2
Memory
Controller
European Space Agency</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> AHB/APB
Bridge
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Leon3
Debug Support
Unit
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> 10/100
Mbit Ethernet
MAC
Opencores</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Generic
APB
UART
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Multi-processor
Interrupt Ctrl Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Modular
Timer
Unit
Gaisler Research</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"> Use
command 'info sys' to print a detailed report of attached cores</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">grmon[grlib]>
info sys</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">00.01:003
Gaisler Research Leon3 SPARC V8 Processor (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb master 0</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">01.01:007
Gaisler Research AHB Debug UART (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb master 1</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
apb: 80000700 - 80000800</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
baud rate 115200, ahb frequency 25.00</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">02.01:012
Gaisler Research Simple 32-bit PCI Target (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb master 2</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">03.08:005
Opencores 10/100 Mbit Ethernet MAC (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb master 3</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">00.04:00f
European Space Agency LEON2 Memory Controller (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb: 00000000 - 20000000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb: 20000000 - 40000000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb: 40000000 - 80000000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
apb: 80000000 - 80000100</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
32-bit sdram: 1 * 32 Mbyte @ 0x40000000, col 9, cas 2, ref 15.5 us</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">01.01:006
Gaisler Research AHB/APB Bridge (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb: 80000000 - 80100000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">02.01:004
Gaisler Research Leon3 Debug Support Unit (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb: 90000000 - a0000000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
AHB trace 64 lines</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
CPU#0 win 8, hw breakpoints 2, itrace 64 lines</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
icache 1 * 4 kbyte, 32 byte/line</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
dcache 1 * 4 kbyte, 32 byte/line</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
stack pointer 0x41fffff0</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">05.08:005
Opencores 10/100 Mbit Ethernet MAC (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
irq 12</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
ahb: fffb0000 - fffb1000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">01.01:00c
Gaisler Research Generic APB UART (ver 1)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
irq 2</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
apb: 80000100 - 80000200</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
baud rate 38400, DSU mode</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">02.01:00d
Gaisler Research Multi-processor Interrupt Ctrl (ver 1)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
apb: 80000200 - 80000300</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">03.01:011
Gaisler Research Modular Timer Unit (ver 0)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
irq 8</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
apb: 80000300 - 80000400</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
16-bit scaler, 2 * 32-bit timers, divisor 25</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">grmon[grlib]>
lo /home/jiri/samples/stanford</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">section:
.text at 0x40000000, size 60688 bytes</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">section:
.data at 0x4000ed10, size 2080 bytes</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">section: .jcr
at 0x40026728, size 4 bytes</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">total size:
62772 bytes (94.3 kbit/s)</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">read 192
symbols</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">entry point:
0x40000000</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">grmon[grlib]>
run</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Starting</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
Perm Towers Queens
Intmm Mm Puzzle
Quick Bubble Tree FFT</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">
67 100
67 67
2233 550
67 83
417 2650</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Nonfloating
point composite is 216</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Floating
point composite is 2044</span><br style="font-family: courier new,courier,monospace;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Program
exited normally.</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">grmon[grlib]></span><br>
<br>
<br>
The LEON3MP test bench includes memory models of both boot-prom, sram
and sdram. To build memory images for these models, do 'make soft' .
Note: this will require that the bare-C compiler for LEON3 is
installed,
and /opt/sparc-elf/bin is added to the PATH.<br>
<br>
<br>
<br>
</span></small>
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