Subversion Repositories mips_enhanced

----------------------- Release 1.0.19-b3188 ---------------------------

2008-09-29      Added T1 Niagara bridge and template designs

2008-09-25      GRUSBHC: To conserve power the core disables the RAMS more
                often on non-FPGA technologies

2008-09-25      GRUSBHC: Some signal names in the in and out types for GRUSBHC
                has changed. The reason is that not all signals were named 
                exactly the same as in the UTMI+ specification. Also all UTMI+
                signals are now present, even those which are always constant.
                Also the input ursti has been removed. See grip.pdf for more
                detailed information.

2008-09-25      GRUSBHC: The core is no longer located in library usbhc but 
                instead in library gaisler. In and out types of the core has
                changed from usbhc_in_type and usbhc_out_type to grusb_in_type
                and grusb_out_type respectively. The package file needed to
                instantiate the core has changed from grusbhc_pkg to grusb.
                See grip.pdf for more detailed information and an example of
                how to instantiate the core.

2008-09-25      GRFPU: Updated Altera and (non-FT) Xilinx netlists.

2008-09-25      GRFPU: Allow use of Module Generator multiplier.

2008-09-24      GRPCI: The amba master interface didn't handle a retry/split
                response on the 1k boundary. One data word was lost. 

2008-09-19      Added Mobile SDR support to SDRAM controller in MCTRL.
                Disabled all power-saving functionality when the mobile 
                generic is set to 0 in DDRSPA, SDCTRL and SDMCTRL

2008-09-19      Added support for .ise file generation for ISE9/10

2008-09-18      GRUSBHC: Improve timing by latching AHB ERROR responses
                during first AMBA response cycle.

2008-09-18      GRFPU: Fix rounding of mantissa and exponent in round up, 
                round to zero, and round down for division and sqrt. 
                The core could also produce denormalized numbers when an 
                underflow occured in single precision division.

2008-09-02      I2CMST: Core did not perform clock synchronization and
                did not differentiate between master clock synchronization and
                slave clock stretch. Affects behavior in multi-master systems.

2008-09-01      GRUSBHC: Conserve power on non-FPGA technologies by disabling
                RAMs when a controller is idle. Added scan test support; 
                disable RAMs when in test mode and scan is enabled.

2008-08-24      LEON3: the processor could change address after a retry
                or split response.

2008-08-15      GRPCI & PCIF: Added possibility to drive pci_rst if in host slot

2008-08-08      GRUSBHC: The 'Port Enable/Disable Change' bit in the UHCI PORTSC
                register was set every time the 'Port Enable/Disable' bit 
                changed.

2008-08-08      GRFPU: Rounding of infinity always regarded infinity as created
                from finite operands and the result was thus determined by the 
                rounding rules for the overflow exception.

2008-08-01      LEON3: uncache byte access (LDUBA with ASI=1) could fail on 
                non-FT system without MMU.

2008-07-30      Reduced the address width from 11 to 9 bits of the input
                and output syncram buffers of the usbdcl

2008-07-30      New template design for the Xilinx XtremeDSP Starter platform,
                Spartan-3A DSP 1800A Edition. www.xilinx.com/s3adspstarter

2008-07-30      DDR2SPA now supports Xilinx Spartan 3 devices

2008-07-27      Added dynamic leon3 reset vector option

2008-07-23      Added SPI memory controller (SPIMCTRL) that maps memory
                devices with a serial peripheral interface into AMBA
                address space.

2008-07-22      Added generic (regoutput) to the DDR controller to enable 
                register on output signals to the PHY. 

2008-07-22      Generated script now explicitly turns off automatic 
                optimization of designs in Modelsim.

2008-07-17      Added template designs for Xilinx ML506 and ML507

2008-07-16      SDCTRL: Extended tRFC timing bits in configuration register
                with the tRP bit when Mobile SDR support is enabled.

2008-07-09      Renamed template design leon3-actel-coremp7 to 
                leon3-actel-proasic3.

2008-07-09      Added GRLIB wrapper for Actel's CoreMP7 processor and a
                CoreMP7/GRLIB bridge (CMP7WRAP/CMP7GRLIB). Added CoreMP7
                template design coremp7-actel-proasic3.

2008-07-03      Added initial DDR support for CycloneIII.

2008-07-03      DDRSPA: Extended tRFC timing bits in configuration register
                with the tRP bit when Mobile DDR support is enabled.

2008-06-27      Improved Altera EEK template design (leon3-altera-ep3c25-eek),
                added VGA and LCD support.

2008-06-24      Added template design for the Altera StratixIII (EP3SL150F1152)
                development board.

2008-06-23      Quartus II flow invoked the Classical Timing Analyzer but did
                not explicitly disable the TimeQuest analyzer.

2008-06-23      Added Stratixiii support to DDR2 controller. Fixed ODT control 
                for DDR2 controller (only enabled during memory-write).

2008-06-19      GRUSBHC: Enhanced host controller could use wrong data buffer
                after processing the asynchronous schedule in NAK throttle mode
                when the only active descriptor was a HS QH with RL field set 
                to a non-zero value.

2008-06-16      SVGACTRL: Dynamic clock registers and generics were documented
                as being specified in ns, the correct unit is ps. Positions in
                status register were wrong in documentation.

2008-06-12      GRFPU: fitos and fitod failed in non-standard mode (%fsr.ns = 1)

2008-05-26      SPICTRL: Added 3-wire mode

2008-05-26      SPICTRL: Last SCK cycle could be short. Delay first SCK
                transition, when CPHA = 0, based on clock scaler setting to 
                guarantee proper setup time on MOSI. Data line could change
                value, in anticipaiton of next transfer, before SCK "change" 
                flank in last cycle for CPHA = 0.

2008-05-25      LEON3/MMU: do not change AHB address if htrans has been set
                to keep strict AHB compliance

2008-05-23      Added separate leon3 design for ML403 board

2008-05-23      DSU3 did not respond with HREADY if unimplemented areas
                were accessed and trace buffers were disabled

2008-05-16      GRSPW2 generic nsync=2 did not function.

2008-05-14      Added support for Mobile DDR/SDR. Added support for CL=3 (CAS
                latency) and fixed duration of preamble for single write in
                DDR controller

----------------------- Release 1.0.18-b2949 ---------------------------

2008-05-13      RTL TAP controller (tap_inferred) did not shift out
                instruction register in SHIFT-IR state.

2008-05-12      Added Leon3 Demonstration design and board support for
                Nios II Embedded Evaluation Kit (leon3-altera-ep3c25-eek)

2008-05-05      Added system test software, UTMI+ and ULPI simulation models 
                for GRUSBHC.

2008-05-05      Added oepol generic to control polarity of output enable
                signal (dctrl), and made the signal work for bi-directional
                UTMI+ interface

2008-05-05      Fixed an unlikely bug in GRUSBHC where the core could continue
                to traverse periodic schedule even though software disabled it

2008-05-05      Fixed an unlikely bug in GRUSBHC where the source for a port
                disable could be lost

2008-04-25      The configuration flash for Avnet-eval-xc4v25/60 board could
                not be programmed due to missing -parallel switch in prom.cmd

2008-04-24      scan signal testrst was not propagated to APB bus.

2008-04-23      Added system test software for SPICTRL and I2CMST

2008-04-20      ncsim failed to bind some Xilinx primitives in unisim library

2008-04-11      Added initial support for odt in ddr2 controller.

2008-04-09      rstgen scan support did not work in async mode.

2008-04-08      Changed clock generators for ax, inferred, proasic, proasic3
                and rhlib18t to handle generics pcien and pcisysclk.

2008-04-07      Changed Altera clock generators to use CLKIN as reference

2008-04-04      leon3: cache snooping could fail in systems with separate
                snoop tags, MMU enabled and non-write through 2-port RAM.

2008-04-01      Enabled use of VHDL libraries in Quartus projects

2008-04-01      Removed usage of non-portable 'echo -e' in scripts

2008-03-30      Added support for ML402/403 boards

2008-03-27      Quartus II could not synthesize SPICTRL

2008-03-20      Added support for HAPS Daughter board: SDRAM_1x1, DDR_1x1, 
                GEPHY_1x1 and BIO1 I/O board.

------------------- Release 1.0.18-b2823 ---------------------------

2008-03-12      Added 256-bit AES option to crypto cores

2008-03-10      APBUART TX FIFO debug register could be accessed from several
                addresses

2008-03-05      Changed a few generics for blocks internal to USBHC that were
                non integers

2008-02-27      Added netlist support for pciarb (for rtax)

------------------- Release 1.0.18-b2808 ---------------------------

2008-02-26:     Added single interrupt support for GRCAN, GRTC and GRCTM

2008-02-26:     Added GRTC interrupt for CLTU stored and added TC input masking

2008-02-26:     Updated GRCTM to avoid false datation after reset

2008-02-21:     LEON3: Added 32-bit multiplier option

2008-02-20:     Removed Ethernet PHY arbiter

2008-02-20:     Added new Ethernet PHY simulation model. Added new
                ethernet test to grlib system test.

2008-02-13:     LEON3: one data cache line could be corrupted on target
                technologies without write-through in tag RAMs, if load
                or store instructions were executed during cache flush.

2008-02-01:     PCIF: fixed handling of retry on last word in fifo, fast
                pci-conf commands, byte/half word accesses to PCI-target.
                Changed size of BAR0 to 4k and added support to set size
                of BAR 1 to 4 separately.

2008-01-31:     Moved testbenches from designs to new verification directory.

------------------- Release 1.0.17-b2738 ---------------------------

2008-01-25:     Changed GRUSBHC so that a SW initiated reset (HC reset for EHCI,
                HC reset and Global reset for UHCI) also resets the USB
                transceiver, and added a generic to control the length of this
                reset.

2008-01-25:     Fixed a bug where GRUSBHC might not detect when software removes
                a data structure from the schedule.

2008-01-21:     Changed edcl init fsm in greth_gbit so that it works both
                with National and Marvell PHYs.

2008-01-18:     GRUSBHC configured the PHY registers wrong which could lead to
                USB power failure not beeing detected.

2008-01-18:     Actel Libero implementation flow fully functional with v8.1

2008-01-17:     unisim syncram had multiple drivers for sizes larger than 64 Kbyte

------------------- Release 1.0.17-b2717 ---------------------------

2007-12-12:     Greth_gbit now only checks/sets speed/duplex when edcl is enabled

------------------- Release 1.0.17-b2710 ---------------------------

2007-12-07:     Reduced Xilinx block RAM usage for small syncram and syncram_2p

2007-12-07:     Fifo write counter was corrupted in greth_gbit when checksum
                offloading was enabled for non ip packet.

2007-12-06:     Added Actel ProASIC3 support to JTAG TAP controller

2007-12-06:     Updated TMTC cores and examples to use GRLIB/AMBA/DMA2AHB package.

2007-12-05:     Leon3 fixed cache mapping ('cached' generic) only affected
                the data cache, not the icache

2007-12-04:     SDRAM controller (MCTRL/SDCTRL) can now operate up to 166 MHz

2007-11-30:     Added tech mapping for eASIC Nextreme 90 nm eRAM and bRAM

2007-11-28:     Added APBUART debug mode with internal read/write capability of TX/RX FIFO

2007-11-23:     Added support for HAPS-52 and HAPS-54 boards, updated HAPS IP cores
                and Xilinx VHDL netlists for ssrctrl

2007-11-20:     Added I2C slave

2007-11-15:     Fixed bug in GRUSBHC (unlikely to occur) where a device connect
                could go undetected.

2007-11-14:     Changed GRUSBHC so that it handles when the USB PHY behaves out-of-spec
                and reports the wrong device speed at connect.

2007-11-12:     Added board support and template design for Gleichmann
                HPE-MIDI board (Stratix-II)

2007-11-12:     leon3: added option for zero-latency TLB look-up
                during stores with cache hit

2007-11-12:     leon3 TLB LRU replacement did not implement LRU correctly,
                leading to sub-optimal TLB replacement

2007-11-09:     Added support for Hardi/Synplicity HAPS boards

2007-11-08:     usbhc_net.vhd still used old usbhc port map (with
                csn, fault etc. signal)

2007-11-08:     Added four GRUSBHC VHDL netlists, for Xilinx

2007-11-07:     GRUSBHC did not handle delayed AHB RETRY/SPLIT/ERROR
                responses correctly.

2007-11-06:     AHB master index for GRETH was not correct set in
                leon3-gr-cpci-xc2v6000 designs.

2007-11-06:     Changed clock generation in DDR2 PHY
                (Old option could in some situations prevent the DCM to lock)

2007-11-02:     MCTRL and FTMCTRL could fail on byte write in 16-bit bus
                configuration with read-modify-write enabled.

------------------- Release 1.0.17-b2594 ---------------------------

2007-10-31:     Added tech mapping for Virage 90 nm RAM blocks

2007-10-31:     Fixed bugs and added standard device requests for USB DCL.
                It now passes the device compliance test.

2007-10-28:     Suppress snoop enable bit in leon3 dcache when snooping
                is disabled in configuration

2007-10-25:     Added new scriptable PCI test master pcitb_master_script
                Example testbench (designs/pci/script_tb)

2007-10-22:     Added tech mapping and PLL support for DARE 0.18 um

2007-10-19:     Improved behaviour of LDA with ASI=0x01 (forced miss).
                LDA with ASI=0x01 does not allocate a cache line now.
                Caches could not be frozen on interrupt.

2007-10-18:     Fixed bug in GRUSBHC (unlikely to occur) where the UHC
                could get stuck in port resume if SW behaved out-of-spec

2007-10-17:     Added leon3 template design for Xilinx ML501 board

2007-10-17:     Improved Proasic3 tech mapping to support PLL.

2007-10-15:     Added tech support for CylconeIII FPGAs, including
                leon3 template design for Altera NiosII CycloneIII board

2007-10-08:     Added tech support for Quicklogic Eclipse FPGAs

2007-10-08:     Improved synchronization in JTAG Debug Link.

2007-10-05:     Active level of GRUSBHC signals drvvbus and vbusvalid, used
                in UTMI+ interface, is configurable through generics

2007-10-05:     Signals fault, faultn, enablen, vbus, csn, id was removed from
                GRUSBHC core since they are not ULPI signals but chip specific

2007-10-05:     Txfifosize was not set correctly when edcl generic was set to 2

2007-10-05:     AHB/AHB bridge: Interrupt forwarding and read burst to
                non-prefetchable area could fail. All types of AHB
                bursts are now supported.

2007-09-27:     Moved USBHC to separate library, GRLIB wrapper added
                under gaisler/grusbhc.

2007-09-27:     GRUSBHC supports 8-bit and 16-bit UTMI+ interface

2007-09-24:     Greth and greth_gbit did not handle retry/split correctly.

2007-09-24:     Corrupt packets with incorrect length in type field could
                cause a deadlock in greth.

2007-09-24:     Reduced block RAM use in EDCL. Maximum fifosize
                increased for greth

2007-09-24:     Corrected the number of interrupts in plug&play printout
                for GRCTM

2007-09-24:     Extended pcilib addzero constant to 32-bits to support
                larger decoded areas

2007-09-24:     Added 16-bit PROM/IO support to SSRCTRL

2007-09-21:     Added LEON3-RTAX pinout for Ethernet support and multiple
                PCI interrupts

2007-09-20:     Board support and template design for Hardy HAPS51 board

2007-09-14:     Renamed tech library apa3 to proasic3

2007-09-13:     pci_mtf could respond with an unecessary retry cycle
                during target writes

2007-08-31:     Changed how GRUSBHC turns on/off port power for ULPI chips, now
                it also works with transceivers that use DRVVBUS and
                DRVVBUS_EXTERNAL the other way around from what ULPI spec. says

2007-08-29:     Changed split transaction isochronous IN max packet size
                from 188 to 192 bytes in GRUSBHC.

2007-08-28:     Corrected 8-bit EDAC support for multiple PROM banks in FTSRCTRL

2007-08-27:     Board support and template design for Hardy HAPS31 board

2007-08-27:     Board support and template design for Xilinx ML505 board
                bow support DDR2 at 200 MHz (DDR400).

2007-08-24:     Added DDR2 Controller and PHY for virtex-4/5

2007-08-22:     Added ucf file for gr-4m-can2-spw3 mezzanine to the
                gr-cpci-xc2v board

2007-08-22:     leon3-avnet-ml401 template design could not be
                synthesized without Gigabit GRETH and GRUSBHC.

2007-08-22:     Added Greth wrapper with blockrams but without port records
                and plug and play

2007-08-21:     Board support and template design for Actel COREMP7-1000 board

2007-08-20:     Added SPI controller

2007-08-17:     Added GRSPW2

2007-08-17:     Moved GRETH to separate library

2007-07-30:     DSU AHB trace buffer index register was written with
                wrong bits when accessed by software.

2007-07-20:     LEON3: a sequence of two consecutive JMP/JMPL would fail
                to execute the target instruction of the first JMP.

2007-07-05:     All SR and SD memory controllers updated with "HSPLIT < (others => '0');" statement

2007-07-05:     FTSRCTRL updated to avoid latching the address when other slaves are accessed

2007-06-29:     Added port of OC I2C-master

2007-06-29:     Added USB host controller testbench

------------------- Release 1.0.16-b2313 ---------------------------

2007-06-27:     Writing MMU contex register through DSU could corrupt
                other MMU registers.

2007-06-20:     Added option to add custom JTAG ID to tap controller

2007-06-20:     Added scan test signals to AHB/APB records

2007-06-20:     Added scan support for PCI_MTF, GRETH and FTMCTRL

2007-06-20:     Worked around synplify-8.8 issue in Altera DDR PHY

2007-06-18:     GRPCI - Added support for type 1 configuration cycles
                      - Configurable AHB slave size (128 MB - 2 GB)

2007-06-08:     Added number of channels information to GRHCAN, no effect for standard single channel designs

2007-06-08:     GRFIFO extended with status register, and support for single interrupt and registers with singleirq vhdl generic

2007-05-28:     Added reset to GRGPIO output flip-flops

2007-05-25:     Added USB 2.0 Host Controller (commercial only)

2007-05-16:     Second port added to GRSPW

2007-05-15:     Added GRPCI CBE tests (designs/pci/cbe_tb)

2007-05-12:     GRPCI core now supports byte enable changes during PCI bursts.

2007-05-09:     Added busreset IRQ to BRM wrappers

2007-05-07:     Made grant signal registered in BRM AHB master interface
                Made waitn signal registered in asynchronous BRM wrapper

------------------- Release 1.0.15-b2180 ---------------------------

2007-05-06:     Added VHDL netlists of GRSPW, GRFPU-Lite and LEON3FT.

------------------- Release 1.0.15-b2172 ---------------------------

2007-04-29:     Added board support and template design for new
                Pender GR-CPCI-XC4V Virtex4-LX100 board

2007-04-28:     Added board support and template design for
                Xilinx ML505 Virtex5-LX50T board

2007-04-27:     B1553BRM did not propagate betiming generic to BRM core

2007-04-23:     Added input/output register bypass capability to GRGPIO

------------------- Release 1.0.15-b2149 ---------------------------

2007-04-19:     Added support to skip unused libraries and files from
                being included into build scripts

2007-04-17:     Added tech mapping for IHP 0.25 rad-hard library

2007-04-16:     Improved coverage of cache snooping in SMP systems for
                fast snooping option

------------------- Release 1.0.15-b2133 ---------------------------

2007-04-07:     Added custmom memory controller to Avnet Spartan3
                template design in order to support mezzanine board.

2007-03-30: Updated GRLIB/DMA2AHB master interface to issue HSIZE synchronously with HADDR

2007-03-30:     Added initial support for Virtex5

2007-03-30:     Added Hynix and Micron DDR2 simulation models

2007-03-30:     Improved implementation of LEON3 double-clock option
                + added new features (dynamic clock switching, double
                clocked cores can run at 2x, 3x or 4x AHB freq)

2007-03-25:     Added support for MINGW shell as development env.

2007-03-25:     Modified SDRAM controllers to use 8-word bursts
                in addition to page bursts

2007-03-22:     Added SatCAN wrapper and CAN bus multiplexer

2007-03-09:     Added support for Actel Libero-7.3, using the
                'make libero-launch' target

2007-03-07:     PCIDMA did not handle memory accesses to slow memory
                (>2 waitstates) correctly when retry was received
                from the PCI-core. One word was not transfered.

2007-03-07:     DSU registers could not be read with AHB burst

2007-03-07:     DSU diagnostic write to instruction trace buffer
                used wrong word address

2007-03-07:     EDAC did not work correctly in ftsrctrl when prom8en
                generic was 0.

------------------- Release 1.0.14-b2053 ---------------------------

2007-02-26:     Added clock-gating power-down option for LEON3

2007-02-23:     AMBA monitor split into AHB and APB parts which are
                integrated into ahbctrl and apbctrl.

2007-02-23:     Improved implementation of LEON3 double-clock option

2007-02-22:     MCTRL/FTMCTRL memo.bdrive did not change polarity
                when OEPOL = 1

2007-02-22:     LEON3 ML401 template design used duplicate interrupt
                for PS/2 ports

------------------- Release 1.0.14-b2037 ---------------------------

2007-02-20:     Added tech mapping for Artisan RAMs

2007-02-19:     Physical cache snooping in leon3 MMU did not work
                with multi-way caches

2007-02-17:     Always enable broadcast function in IRQMP controller
                if NCPU > 1.

------------------- Release 1.0.14-b2028 ---------------------------

2007-02-13:     Avoid AHB lock-up by inserting idle cycle between two
                consecutive accesses which assert HLOCK (leon3).

2007-02-12:     Added option to break processor on AHB trace buffer hit.

2007-02-10:     The delay counter in Leon3 DSU AHB trace buffer should
                decrement each AHB transfer, not each clock.

2007-02-10:     Added AMBA AHB/APB protocol monitor (commercial only)

2007-02-06:     Applicable bugfixes from ftmctrl merged to mctrl.

2007-02-01:     Several bugfixes to ftmctrl. 8-bit edac addressing
                changed for ftmctrl.

2007-01-24:     Implemented snooping for MMU data cache, enabling
                support for linux SMP on kernel 2.6.18

2007-01-23:     LEON3 scratch pad RAM size was wrongly defined in
                cache config registers

2007-01-22:     GRPCI target did not handle AMBA 1 Kbyte limit correctly

2007-01-16:     Added template design for Digilent spartan3-1000

2007-01-15:     Added support for Aldec VHDL simulators

2007-01-05:     Modified Xilinx DDR PHY to allow extra skew for
                read clock phase adjusting.

2006-12-24:     Added template design for Digilent spartan3e-1600

2006-12-23:     Added techmap support for Xilinx spartan3e, including
                DDR PHY.

2006-12-22:     Wrong drive strength and I/O type on some Xilinx pads

2006-12-19:     Added missing video clock in leon3-gr-xc3s-1500 design

2006-12-18:     DDRSPA core had wrong DDR initialization sequence

2006-12-11:     Re-write of the PS/2 core due to several bugs

------------------- Release 1.0.13 ---------------------------------

2006-12-04:     LEON3 DSU break signal was active on falling
                edge instead of rising edge.

2006-12-04:     Improved read-datapath synchronisation for Xilinx
                verion of DDRSPA PHY to achieve 120 MHz operation

2006-11-30:     LEON3 MMU could incorrectly update fault status
                register on a TLB flush

2006-11-30:     Removed option to invert SDRAM clock from clkgen,
                as it is no longer needed.

------------------- Release 1.0.12 ---------------------------------

2006-11-29:     GRSPW DMA write could fail if last data was not
                word aligned and received an AHB retry or split.

2006-11-28:     PCI bridge could miss a target access on simultaneous
                target and initiator requests.

2006-11-24:     Added optional JTAG DSU interface to all Altera-based
                template designs.

2006-11-20:     Added support and template design for Altera
                Straix-II EP2S60 board with SSRAM and DDR

2006-11-19:     Modifed template design for Avnet Virtex4 Eval board
                to support both LX25 and LX60 devices.

2006-11-17:     Added support for Altera Virtual JTAG controller
                to AHBJTAG DSU interface

2006-11-09:     Improve coverage of cache snooping in SMP systems

2006-11-09:     LEON3 could assert HLOCK one cycle too late for SWAP

2006-11-04:     Added support and template design for Memec V2MB1000
                board, including 16-bit DDR and P160 mezz. with ethernet

2006-11-03:     New implementation of GRPCI DMA controller

2006-11-02:     Added new SVGA video frame buffer with AHB master I/F,
                capable of 640x480, 800x600 and 1024x768 with 8-,
                16- and 32-bit colour depth.

2006-10-31:     Added support and template design for Altera
                Straix-II EP2S60 board with SDRAM

------------------- Release 1.0.11 ---------------------------------

2006-10-23:     Added pre-compiled netlists of USB-2.0 DSU interface

2006-10-21:     Added board support and template design for
                Digilent XUP board, including 64-bit DDR controller

2006-10-20:     AHB controller could loose interrupt when processing
                SPLIT transactions

2006-10-18:     Added new version of GRETH MAC with giga-bit capability,
                TCP checksum off-loading and scatter-gather DMA

2006-10-15:     Added new 32-bit DDR266 controller to ML401 template design

2006-10-10:     Added board support and template design with 16-bit DDR
                for Avnet Virtex4 LX25 Eval board

2006-10-08:     Added new 16/32/64-bit DDR266 controller with
                separate clocking and modular DDR PHY

2006-10-01:     GRPCI - Added support for byte-swapping
                      - Added interrupt support
                      - AHB slave interface did not handle back2back transfers
                      - AHB master fifo read out synchronization fix
                      - PCI master did not always terminate write bursts
                        at correct length

2006-09-18:     SDRAM clock generation was disabled by mistake
                in leon3-gr-xc3s-1500 template design

2006-09-01:     GRETH MAC could loose data after excessive AHB retries

2006-08-31:     All generics did not propagate in pci_mtf core

------------------- Release 1.0.10 ---------------------------------

2006-08-28:     Worked-around some XST synthesis bugs in leon3 MMU

2006-08-20:     Corrected FIFO/DMA errors in the GRPCI core

2006-08-18:     Modified the SDRAM inverted clock option to delay SDRAM
                signals rather than then inverting the clock

2006-08-17:     Improved SDRAM controller timing to meet PC133

2006-08-12:     Added RMII interface to GRETH ethernet MAC

2006-07-20:     Added preliminary Libero-7.2 project file generation.
                Does not work yet due to Libero bugs though ...

2006-06-15:     Leon3 locked transfers could fail after a cache burst

------------------- Release 1.0.9 ----------------------------------

2006-07-04:     Added support for the LAN91C111 ethernet MAC in
                the Altera Cyclone/Nios template design

2006-06-07:     Added ATA and CF+ interface to applicable template designs

2006-06-05:     Added ATA disk controller with AHB interface

2006-05-30:     Leon3 data forwarding could (in theory) fail during
                first trap instruction

2006-05-27:     Added support for Actel Libero

2006-05-25:     Added USB-2.0 debug communication link

2006-05-20:     Added support for Mentor Precision synthesis tool

2006-05-03:     Cache snooping could fail during cache miss processing

2006-04-29:     DDR controller also ported to Lattice EC/P

2006-04-15:     GRETH MAC debug link could loose and/or duplicate packets

------------------- Release 1.0.8 ----------------------------------

2006-03-29:     Added 2-port, 32-bit DDR controller for Virtex2/4 and Lattice

2006-03-29:     Added DDR clock generator for Virtex2/4 and Lattice

2006-03-29:     EXTRALIBS in Makefile can point to secondary libs.txt

2006-03-29:     Leon3 fast snooping option was never enabled by xconfig

2006-03-20:     Added new 32-bit ZBT SSRAM memory controller

2006-03-20:     Simulation model of SSRAM allows srecord pre-load

2006-03-20:     Added template design for Avnet Virtex2-1500 PCI board

------------------- Release 1.0.7 ----------------------------------

2006-02-26:     Added CAN interface to GR-XC3S-1500 design

2006-02-23:     Added uni- and bi-directional AHB/AHB Bridge

2006-02-23:     CAN core bug fixes + new data sheet

2006-01-20:     Timing improvements in GRSPW Spacewire core

2006-01-20:     Chain mode in gptimer chained with wrong timer

2006-01-20:     Moved all vendor/device ID codes to grlib.devices

2006-01-09:     pci_mtf core could not handle 0-ws AHB slaves

2006-01-09:     config.in script for VGA controller never enabled the core

2006-01-08:     modified leon3-gr-cpci designs to use correct clocks

2006-01-05:     TMTC updated to current version of grlib. DMA2AHB improved.

2006-01-05:     added 32-bit addresses to memory controllers

2006-01-05:     gptimer watchdog did not reset properly at power-on


------------------- Release 1.0.6 ----------------------------------

2005-12-29:     grfpwx.vhd was missing in ISE/XST script files

2005-12-27:     Added LEON3 template design for ML401 Virtex4 board

2005-12-27:     Added Virtex4 support to JTAG TAP controller

2005-12-27:     Added simulation model of MT46V16M16 DDR RAM

2005-12-21:     Added simulation model of CY7C1354B Synchronous SRAM

2005-12-21:     Added Reed-Solomon Codecs for 16/8 and 32/16 codes

------------------- Release 1.0.5 ----------------------------------

2005-12-20:     Re-organized technology mapping libraries

2005-12-18:     Added support for Lattice XP/EC/ECP

2005-12-18:     Added support for Xilinx Virtex-4 JTAG controller

2005-12-07:     Added new 10/100 Mbit Ethernet MAC (GRETH)

2005-12-05:     LEON3-GR-PCI-XC2V template design would not simulate
                correctly due to unsupported frequency scaling. Also,
                test bench would fail if Spacewire link not present.

------------------- Release 1.0.4 -----------------------------------

2005-11-28:     Moved all technology mapped blocks to new TECHMAP library.

2005-11-24:     UMAC/SMAC with pipe option (v8 = 2) did not check
                dependency on result register.

2005-11-21:     Modified watchdog output on GPTIMER to be sticky.

2005-11-13:     On-chip logic analyzer (LOGAN) support software did not
                properly display non-binary aligned trace buffer widths.

2005-11-11:     Wrong chip-select generated by SDRAM controller in
                MCTRL for 512 Mbyte bank size

2005-11-09:     Added VHDL version of Opencores CAN core;

2005-11-10:     Nuhorizon spartan3 design no loner needs inverted
                sdram clock due to improved clock generation

2005-10-25:     Added spacewire support to GR-XC3S-1500 board and other
                design templates

2005-10-25:     Added GRSPW spacewire core with RMAP support

2005-10-24:     Added AMBA wrappers for Actel 1553 BC/RT/BRM cores

2005-10-10:     Extended default AMBA interrupt vector width to 32 bits

2005-10-10:     Added template design for Gleichmann HPE-MINI Lattice board

2005-10-01:     GRGPIO I/O port would drive all outputs on reset
                if generic OEPOL = 1.

2005-09-30:     leon3 test bench could fail due to unmasked interrupts

2005-09-28:     updated altera clock generator to correctly calculate
                clock period from frequency

2005-09-28:     swapped read/write ports on altera syncram_2p to
                work-around bug in Cyclone-2 fpgas

2005-09-20:     Fixed faulty ip header checksum initialization for edcl

2005-09-19:     virage ram model should not disable output when chip-select
                is de-asserted

------------------- Release 1.0.3 -----------------------------------

2005-09-11:     Updated Altera template designs to use new RAM mapping

2005-09-09:     Added Altera RAM mapping (altsyncram)

2005-09-09:     Added template design for Altera Cyclone Eval board

------------------- Release 1.0.2 -----------------------------------

2005-09-06:     Worked around GHDL bug in gptimer, GHDL can now simulate
                complete library and template designs

2005-09-06:     Improved SMP control LEON3 SMP systems

2005-09-02:     Improved LEON3 bus request generation for non-overhead
                bus re-arbitration

2005-09-02:     AHB arbiter now supports all transfer types according
                to the AMBA standard.

2005-08-15:     Added generation of ISE-7.1 project files

2005-07-26:     New PS2 keyboard core

2005-07-26:     New text-based VGA video controller

2005-07-08:     New on-chip logic analyzer core

------------------- Release 1.0.1 -----------------------------------

2005-06-03:     Allow local ram to be 512 Kbyte

2005-05-31:     Allow cache set and local ram to be 256 Kbyte

2005-05-27:     PCI device and vendor id were not handled as hex values
                in template designs

2005-05-24:     decrease block ram usage for DSU trace buffers on
                virtex2 and spartan3 targets

2005-05-20:     Leon3 MMU LRU replacement did not work correctly

2005-05-13:     Fixed wrong bitgen parameters for gr-xc3s-1500 board

2005-05-13:     removed absolute path to synplify in global makefile

------------------- Release 1.0.0 -----------------------------------

2005-04-20:     Added individual interrupt force register to SMP irq controller

2005-04-20:     Support and template design for GR-CPCI-AX AX/RTAX2000 board

2005-04-19:     Support and template design for GR-XC3S-1500 spartan3 board

2005-04-08:     Improved reset of LEON3 to allow gate-level simulation

2005-04-04:     Added new leon3/grlib generic test bench

2005-03-30:     Added IHP 0.25 um technology and template design

2005-03-24:     Improved scripts for place&route with Actel Designer

2005-03-17:     added support for Gleichmann HPE-MINI board + template design

2005-03-07:     added interrupt filtering to GRGPIO module

2005-03-04:     changed from 2 to 8 refresh cycles in sdctrl initialisation

2005-02-28:     beta-0.16 released

2005-02-27:     Added clock pad for xilinx devices

2005-02-23:     Added support for AHB fixed lentgh bursts to LEON3

2005-01-09:     Added macros for prom generation to board makefiles

2005-01-09:     Added clock-specific pad

2005-01-09:     Added tech port for RH-UMC 0.18 um

2004-12-26:     Improved pad mapping for Xilinx parts

2004-12-26:     Added byte enable signals to sram memory controllers.

2004-12-26:     Added simulation models for 16-bit sram/prom with UB/LB
                byte enable signals.

2004-12-24:     Support for Avnet Spartan3 Evaluation board, adding board
                templates and a leon3 reference design (leon3mp-avnet-3s1500).

2004-12-15:     beta-0.15 released

2004-12-14:     leon3 instruction scratch pad ram added

2004-12-14:     Graphical GUI for implementation

2004-12-14:     New makefile system

2004-12-14:     leon3 MMU added

2004-12-14:     Support for Quartus GUI including synthesis

2004-12-14:     Support for Xilinx ISE project navigator

2004-12-05:     Support for Altera PLL (altpll)

2004-11-19:     OpenCores CAN core added

2004-11-01:     leon3 diagnostic cache access failed for multi-set caches

2004-11-01:     Added reset delay for Xilinx DCM/DLL to allow simulation
                with Xilinx unisim models

2004-11-01:     leon3 watchpoints were not properly reset

2004-10-27:     leon3 power-down mode added

2004-10-27:     Added CCSDS convolutional encoder/decoder IP

2004-10-11:     ESA mctrl.vhd did not support brdyn streaching for ramsn(4)
                in 8- and 16-bit bus configurations

2004-10-10:     Removed Opencores PCI bridge since it doesn't fully work and
                we have the Gaisler bridge anyway

2004-10-07:     Add optional timing improvement to Actel AX regfile by
                hardwiring read enable signals