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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [misc/] [ahbram.in.help] - Rev 2
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On-chip ram
CONFIG_AHBRAM_ENABLE
Say Y here to add a block on on-chip ram to the AHB bus. The ram
provides 0-waitstates read access and 0/1 waitstates write access.
All AHB burst types are supported, as well as 8-, 16- and 32-bit
data size.
On-chip ram size
CONFIG_AHBRAM_SZ1
Set the size of the on-chip AHB ram. The ram is infered/instantiated
as four byte-wide ram slices to allow byte and half-word write
accesses. It is therefore essential that the target package can
infer byte-wide rams. This is currently supported on the generic,
virtex, virtex2, proasic and axellerator targets.
On-chip ram address
CONFIG_AHBRAM_START
Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
a 1 Mbyte slot at the selected address. Default is A00, corresponding
to AHB address 0xA0000000.