Subversion Repositories mod_mult_exp

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#!/bin/sh
 
rm -rf simv* csrc DVEfiles AN.DB
 
echo "Compiling Core VHDL UNISIM/Behavioral model"
vhdlan  ../../implement/results/routed.vhd
 
echo "Compiling Test Bench Files"
vhdlan    ../bmg_tb_pkg.vhd
vhdlan    ../random.vhd
vhdlan    ../data_gen.vhd
vhdlan    ../addr_gen.vhd
vhdlan    ../checker.vhd
vhdlan    ../bmg_stim_gen.vhd
vhdlan    ../blockMemory_synth.vhd 
vhdlan    ../blockMemory_tb.vhd
 
 
echo "Elaborating Design"
vcs +neg_tchk -sdf max:/blockMemory_tb/blockMemory_synth_inst/bmg_port:../../implement/results/routed.sdf +vcs+lic+wait -debug blockMemory_tb
 
echo "Simulating Design"
./simv -ucli -i ucli_commands.key
dve -session vcs_session.tcl