Subversion Repositories mod_mult_exp

INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
WARNING:sim - A core named 'blockMemory' already exists in the project. Output
   products for this core may be overwritten.
Resolving generics for 'blockMemory'...
WARNING:sim - A core named 'blockMemory' already exists in the project. Output
   products for this core may be overwritten.
Applying external generics to 'blockMemory'...
Delivering associated files for 'blockMemory'...
WARNING:sim - Component blk_mem_gen_v7_1 does not have a valid model name for
   VHDL synthesis
Delivering EJava files for 'blockMemory'...
Generating implementation netlist for 'blockMemory'...
INFO:sim - Pre-processing HDL files for 'blockMemory'...
Running synthesis for 'blockMemory'
Running ngcbuild...
Writing VHO instantiation template for 'blockMemory'...
Writing VHDL behavioral simulation model for 'blockMemory'...
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'blockMemory'...
Generating metadata file...
Generating ISE project...
XCO file found: blockMemory.xco
XMDF file found: blockMemory_xmdf.tcl
Adding E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.asy -view all -origin_type imported
Adding E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.ngc -view all -origin_type created
Checking file "E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.ngc" for project device match ...
File "E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.ngc" device information matches project device.
Adding E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.sym -view all -origin_type imported
Adding E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.vhd -view all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file "E:/spent i
   praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp
   /_cg/blockMemory.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding E:/spent i
praca/OpenCores/ModMultExp_opencores_edition/rtl/vhdl/mod_exp/blockMemory/tmp/_c
g/blockMemory.vho -view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/blockMemory"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'blockMemory'.