Subversion Repositories mod_mult_exp

 
 
 
 
 
 
 
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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--------------------------------------------------------------------------------
--
-- Filename: blockMemory_exdes.vhd
--
-- Description:
--   This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
 
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blockMemory_exdes IS
  PORT (
      --Inputs - Port A
    RSTA           : IN STD_LOGIC;  --opt port
 
    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ADDRA          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
 
    DINA           : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
 
    DOUTA          : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    CLKA       : IN STD_LOGIC
 
 
  );
 
END blockMemory_exdes;
 
 
ARCHITECTURE xilinx OF blockMemory_exdes IS
 
  COMPONENT BUFG IS
  PORT (
     I      : IN STD_ULOGIC;
     O      : OUT STD_ULOGIC
  );
  END COMPONENT;
 
  COMPONENT blockMemory IS
  PORT (
      --Port A
    RSTA       : IN STD_LOGIC;  --opt port
 
    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ADDRA      : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
 
    DINA       : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
 
    DOUTA      : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
 
    CLKA       : IN STD_LOGIC
 
 
 
  );
  END COMPONENT;
 
  SIGNAL CLKA_buf     : STD_LOGIC;
  SIGNAL CLKB_buf     : STD_LOGIC;
  SIGNAL S_ACLK_buf   : STD_LOGIC;
 
BEGIN
 
  bufg_A : BUFG
    PORT MAP (
     I => CLKA,
     O => CLKA_buf
     );
 
 
 
  bmg0 : blockMemory
    PORT MAP (
      --Port A
      RSTA       => RSTA,
 
      WEA        => WEA,
      ADDRA      => ADDRA,
 
      DINA       => DINA,
 
      DOUTA      => DOUTA,
 
      CLKA       => CLKA_buf
 
 
    );
 
END xilinx;