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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory64/] [blockMemory_beh.cgp] - Rev 5

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# Date: Sat Dec 22 01:24:09 2012

SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = .\tmp\

# CRC: 46f7aa00

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