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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML><HEAD> <TITLE>Analysis & Synthesis Resource Utilization by Entity</TITLE> <link rel="stylesheet" type="text/css" href="css/reset.css"> <link rel="stylesheet" type="text/css" href="css/base.css"> <link rel="stylesheet" type="text/css" href="css/jquery-ui.css"> <link rel="stylesheet" type="text/css" href="css/jquery.layout-latest.css"> <link rel="stylesheet" type="text/css" href="css/override.css"> <script type="text/javascript" src="js/jquery.min.js"></script> <script type="text/javascript" src="js/jquery-ui.min.js"></script> <script type="text/javascript" src="js/jquery.layout-latest.js"></script> </HEAD> <BODY> <TABLE> <thead><TR bgcolor="#BFBFBF"> <TH>Compilation Hierarchy Node</TH> <TH>LC Combinationals</TH> <TH>LC Registers</TH> <TH>Memory Bits</TH> <TH>DSP Elements</TH> <TH>DSP 9x9</TH> <TH>DSP 18x18</TH> <TH>DSP 36x36</TH> <TH>Pins</TH> <TH>Virtual Pins</TH> <TH>Full Hierarchy Name</TH> <TH>Library Name</TH> </TR> </thead><tbody><TR > <TD >|mod_sim_exp_core</TD> <TD >13660 (3)</TD> <TD >3700 (0)</TD> <TD >10272</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >125</TD> <TD >0</TD> <TD >|mod_sim_exp_core</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |fifo_generic:the_exponent_fifo|</TD> <TD >36 (36)</TD> <TD >14 (14)</TD> <TD >1056</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|fifo_generic:the_exponent_fifo</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >1056</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|fifo_generic:the_exponent_fifo|dpram_generic:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >1056</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD 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|cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:10:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:11:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:12:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:13:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:14:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:15:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:16:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:17:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:18:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:19:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:1:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:20:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:21:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:22:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</