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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML><HEAD> <TITLE>Analysis & Synthesis Resource Utilization by Entity</TITLE> <link rel="stylesheet" type="text/css" href="css/reset.css"> <link rel="stylesheet" type="text/css" href="css/base.css"> <link rel="stylesheet" type="text/css" href="css/jquery-ui.css"> <link rel="stylesheet" type="text/css" href="css/jquery.layout-latest.css"> <link rel="stylesheet" type="text/css" href="css/override.css"> <script type="text/javascript" src="js/jquery.min.js"></script> <script type="text/javascript" src="js/jquery-ui.min.js"></script> <script type="text/javascript" src="js/jquery.layout-latest.js"></script> </HEAD> <BODY> <TABLE> <thead><TR bgcolor="#BFBFBF"> <TH>Compilation Hierarchy Node</TH> <TH>LC Combinationals</TH> <TH>LC Registers</TH> <TH>Memory Bits</TH> <TH>DSP Elements</TH> <TH>DSP 9x9</TH> <TH>DSP 18x18</TH> <TH>DSP 36x36</TH> <TH>Pins</TH> <TH>Virtual Pins</TH> <TH>Full Hierarchy Name</TH> <TH>Library Name</TH> </TR> </thead><tbody><TR > <TD >|mod_sim_exp_core</TD> <TD >13660 (3)</TD> <TD >3700 (0)</TD> <TD >10272</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >125</TD> <TD >0</TD> <TD >|mod_sim_exp_core</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |fifo_generic:the_exponent_fifo|</TD> <TD >36 (36)</TD> <TD >14 (14)</TD> <TD >1056</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|fifo_generic:the_exponent_fifo</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >1056</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|fifo_generic:the_exponent_fifo|dpram_generic:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >1056</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD 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>|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:0:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:10:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:10:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:11:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:11:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:12:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:12:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:13:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:13:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:14:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:14:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:15:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:15:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:16:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:16:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:17:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:17:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:18:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:18:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:19:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:19:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:1:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:1:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:20:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:20:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:21:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:21:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:22:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:22:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:23:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:23:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:24:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:24:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:25:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:25:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:26:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:26:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:27:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:27:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:28:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:28:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:29:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:29:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:2:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:2:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:30:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:30:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:31:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:31:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:32:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >4 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >77 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:32:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:33:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:33:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:34:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:34:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:35:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:35:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:36:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:36:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:37:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:37:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:38:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:38:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:39:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:39:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:3:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:3:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:40:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:40:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:41:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:41:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:42:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:42:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:43:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:43:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:44:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:44:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:45:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:45:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:46:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:46:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:47:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:47:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:48:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:48:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:49:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:49:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:4:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:4:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:50:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:50:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:51:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:51:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:52:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:52:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:53:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:53:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:54:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:54:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:55:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:55:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:56:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:56:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:57:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:57:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:58:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:58:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:59:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:59:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:5:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:5:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:60:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:60:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:61:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:61:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:62:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:62:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:63:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:63:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:64:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:64:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:65:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:65:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:66:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:66:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:67:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:67:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:68:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:68:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:69:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:69:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:6:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:6:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:70:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:70:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:71:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:71:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:72:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:72:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:73:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:73:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:74:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:74:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:75:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:75:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:76:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:76:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:77:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:77:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:78:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:78:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:79:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:79:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:7:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:7:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:80:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:80:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:81:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:81:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:82:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:82:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:83:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:83:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:84:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:84:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:85:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:85:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:86:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:86:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:87:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:87:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:88:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:88:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:89:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:89:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:8:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:8:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:90:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:90:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:91:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:91:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:92:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:92:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:93:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:93:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:94:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:94:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:95:stage|</TD> <TD >110 (16)</TD> <TD >19 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >14 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >64 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >3 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:95:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |sys_stage:\pipeline_stages:9:stage|</TD> <TD >113 (16)</TD> <TD >22 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:my_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:my_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |adder_block:reduction_adder|</TD> <TD >16 (0)</TD> <TD >1 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:0:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:0:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:10:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:10:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:11:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:11:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:12:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:12:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:13:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:13:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:14:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:14:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:15:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:15:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:1:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:1:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:2:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:2:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:3:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:3:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:4:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:4:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:5:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:5:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:6:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:6:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:7:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:7:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:8:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:8:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:\adder_chain:9:adders|</TD> <TD >1 (1)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|cell_1b_adder:\adder_chain:9:adders</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:carry_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|adder_block:reduction_adder|d_flip_flop:carry_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |d_flip_flop:done_signal|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|d_flip_flop:done_signal</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:cout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|register_1b:cout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:qout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|register_1b:qout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_1b:xout_reg|</TD> <TD >0 (0)</TD> <TD >1 (1)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|register_1b:xout_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |register_n:result_reg|</TD> <TD >0 (0)</TD> <TD >16 (16)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|register_n:result_reg</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |standard_cell_block:sys_cells|</TD> <TD >65 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:0:cells|</TD> <TD >5 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >3 (3)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:0:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:10:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:10:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:11:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:11:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:12:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:12:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:13:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:13:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:14:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:14:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:15:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:15:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:1:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:1:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:2:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:2:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:3:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:3:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:4:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:4:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:5:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:5:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:6:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:6:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:7:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:7:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:8:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:8:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b:\cell_block:9:cells|</TD> <TD >4 (0)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_adder:cell_adder|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_adder:cell_adder</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |cell_1b_mux:cell_mux|</TD> <TD >2 (2)</TD> <TD >0 (0)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|sys_pipeline:systolic_array|sys_stage:\pipeline_stages:9:stage|standard_cell_block:sys_cells|cell_1b:\cell_block:9:cells|cell_1b_mux:cell_mux</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |x_shift_reg:x_selection|</TD> <TD >1537 (1537)</TD> <TD >1536 (1536)</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|mont_multiplier:the_multiplier|x_shift_reg:x_selection</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |operand_mem_gen:the_memory|</TD> <TD >1142 (0)</TD> <TD >0 (0)</TD> <TD >9216</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |modulus_ram_gen:m_ram|</TD> <TD >61 (61)</TD> <TD >0 (0)</TD> <TD >3072</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:0:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:0:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:0:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:0:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:10:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:10:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:10:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:10:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:11:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:11:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:11:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:11:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:12:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:12:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:12:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:12:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:13:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:13:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:13:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:13:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:14:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:14:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:14:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:14:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:15:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:15:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:15:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:15:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:16:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:16:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:16:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:16:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:17:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:17:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:17:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:17:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:18:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:18:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:18:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:18:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:19:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:19:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:19:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:19:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:1:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:1:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:1:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:1:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:20:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:20:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:20:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:20:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:21:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:21:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:21:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:21:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:22:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:22:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:22:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:22:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:23:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:23:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:23:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:23:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:24:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:24:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:24:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:24:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:25:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:25:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:25:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:25:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:26:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:26:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:26:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:26:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:27:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:27:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:27:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:27:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:28:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:28:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:28:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:28:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:29:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:29:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:29:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:29:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:2:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:2:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:2:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:2:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:30:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:30:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:30:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:30:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:31:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:31:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:31:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:31:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:32:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:32:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:32:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:32:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:33:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:33:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:33:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:33:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:34:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:34:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:34:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:34:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:35:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:35:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:35:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:35:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:36:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:36:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:36:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:36:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:37:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:37:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:37:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:37:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:38:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:38:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:38:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:38:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:39:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:39:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:39:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:39:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:3:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:3:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:3:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:3:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:40:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:40:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:40:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:40:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:41:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:41:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:41:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:41:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:42:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:42:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:42:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:42:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:43:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:43:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:43:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:43:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:44:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:44:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:44:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:44:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:45:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:45:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:45:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:45:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:46:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:46:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:46:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:46:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:47:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:47:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:47:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:47:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:4:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:4:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:4:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:4:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:5:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:5:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:5:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:5:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:6:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:6:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:6:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:6:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:7:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:7:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:7:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:7:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:8:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:8:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:8:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:8:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |dpram_generic:\ramblocks:9:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:9:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:9:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_pfm1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >64</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|modulus_ram_gen:m_ram|dpram_generic:\ramblocks:9:ramblock|altsyncram:RAM_rtl_0|altsyncram_pfm1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |operand_ram_gen:xy_ram|</TD> <TD >1081 (1081)</TD> <TD >0 (0)</TD> <TD >6144</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:0:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:0:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:0:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:0:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:10:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:10:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:10:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:10:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:11:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:11:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:11:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:11:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:12:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:12:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:12:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:12:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:13:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:13:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:13:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:13:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:14:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:14:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:14:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:14:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:15:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:15:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:15:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:15:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:16:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:16:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:16:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:16:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:17:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:17:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:17:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:17:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:18:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:18:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:18:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:18:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:19:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:19:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:19:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:19:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:1:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:1:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:1:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:1:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:20:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:20:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:20:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:20:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:21:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:21:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:21:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:21:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:22:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:22:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:22:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:22:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:23:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:23:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:23:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:23:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:24:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:24:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:24:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:24:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:25:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:25:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:25:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:25:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:26:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:26:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:26:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:26:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:27:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:27:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:27:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:27:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:28:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:28:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:28:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:28:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:29:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:29:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:29:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:29:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:2:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:2:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:2:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:2:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:30:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:30:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:30:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:30:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:31:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:31:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:31:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:31:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:32:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:32:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:32:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:32:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:33:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:33:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:33:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:33:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:34:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:34:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:34:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:34:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:35:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:35:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:35:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:35:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:36:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:36:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:36:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:36:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:37:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:37:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:37:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:37:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:38:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:38:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:38:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:38:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:39:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:39:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:39:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:39:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:3:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:3:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:3:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:3:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:40:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:40:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:40:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:40:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:41:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:41:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:41:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:41:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:42:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:42:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:42:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:42:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:43:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:43:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:43:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:43:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:44:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:44:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:44:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:44:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:45:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:45:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:45:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:45:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:46:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:46:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:46:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:46:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:47:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:47:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:47:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:47:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:4:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:4:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:4:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:4:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:5:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:5:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:5:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:5:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:6:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:6:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:6:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:6:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:7:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:7:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:7:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:7:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:8:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:8:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:8:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:8:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |tdpram_generic:\ramblocks:9:ramblock|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:9:ramblock</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram:RAM_rtl_0|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:9:ramblock|altsyncram:RAM_rtl_0</TD> <TD > </TD> </TR> </tbody><tbody><TR > <TD > |altsyncram_ses1:auto_generated|</TD> <TD >0 (0)</TD> <TD >0 (0)</TD> <TD >128</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >0</TD> <TD >|mod_sim_exp_core|operand_mem_gen:the_memory|operand_ram_gen:xy_ram|tdpram_generic:\ramblocks:9:ramblock|altsyncram:RAM_rtl_0|altsyncram_ses1:auto_generated</TD> <TD > </TD> </TR> </tbody></TABLE> <noscript>JavaScript must be enabled to view the report.</noscript> </BODY> </HTML>
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