Subversion Repositories myblaze

Release 10.1.03 Map K.39 (lin64)
Xilinx Map Application Log File for Design 'SysTop'

Design Information
------------------
Command Line   : map -ise
/home/daniel/Sources/myblaze/system/uart_test_top/uart_test_top.ise -intstyle
ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o SysTop_map.ncd
SysTop.ngd SysTop.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
Mapped Date    : Sun Nov 21 23:39:00 2010

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:           391 out of   9,312    4%
  Number of 4 input LUTs:             1,262 out of   9,312   13%
Logic Distribution:
  Number of occupied Slices:            702 out of   4,656   15%
    Number of Slices containing only related logic:     702 out of     702 100%
    Number of Slices containing unrelated logic:          0 out of     702   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       1,277 out of   9,312   13%
    Number used as logic:             1,262
    Number used as a route-thru:         15
  Number of bonded IOBs:                 13 out of     232    5%
    IOB Flip Flops:                       1
  Number of RAMB16s:                     11 out of      20   55%
  Number of BUFGMUXs:                     1 out of      24    4%

Peak Memory Usage:  426 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   3 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "SysTop_map.mrp" for details.