Subversion Repositories myhdl_lfsr

This project contains code which may be used to generate a synthesizable Verilog or VHDL module representing a Galois LFSR of a user-specified width.

Max-cycle tap positions are included for some selected register widths.  These positions can be credited to Roy Ward and Tim Molteno, whose table of tap positions is currently available at http://courses.cse.tamu.edu/walker/csce680/lfsr_table.pdf

Tap positions may be added and modified by editing lfsr_tap_table.py

Sample LFSR modules are made available in the sample_modules/ directory.

To use:
MyHDL must be available to your python installation.  Instructions are available at http://myhdl.org/start/installation.html

A module may be generated by running lfsr_gen.py.  

In its current state, lfsr_gen.py will generate an LFSR module for each width available in the tap table.  Generated LFSRs will have a randomized but constant starting value.  Efforts are planned to make this a bit more customizable from an end-user perspective, but users familiar with python should find it easy to make any necessary modifications.