Subversion Repositories myhdl_lfsr

-- File: generated/lfsr_2048.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_2048 is
    port (
        reset: in std_logic;
        clock: in std_logic;
        lfsr_out: out unsigned(2047 downto 0)
    );
end entity lfsr_2048;
 
 
architecture MyHDL of lfsr_2048 is
 
 
 
 
 
signal reg_internal: unsigned(2047 downto 0);
 
begin
 
 
 
 
 
LFSR_2048_LFSR_LOGIC: process (clock, reset) is
begin
    if (reset = '1') then
        reg_internal <= unsigned'"00010110110110011001111110000111000110000001111101110011011100100001001011110001001011000000111010110100110001001100101100100100110000111110011111111001000011010011000100101001101001101000101011100000110011010011011010111111000100101100100101011001001101110100110100100010110110101110011101011010111010111001111111110101110000100110100101110101011101101011111111011000011100101100111100100000100101000010001000010000110111111001110111000001110100010001001111111101011111101101110000000111000100101011010000101110110111001100111100011111110011000011111100101001111100110100110100111011101010011001000011101100010001101101011101011111011000100001100010011000010101010101110100101111101011000111101101101110011101110101001001010010001100000100110100000110100000101001100101011101010011001110101001100000000101011000011101101110110110110100000110101010001111110010000011111101010010110001001101111000001111011011001111010000000000110001101101100110010101001101100110001110100000000111001110111110010000101110010011100111000100100111010100111100000111111100110011110101100111100011000010000111000001010111010011001011110001010011111011101101101001100111110011011011011010111100111000111101111010101011111000111001110101110110110011111111011010100111101011001100110001010111000111000011110010011101000010001111111111000100101111101101110101111101010011110001100011100101010001110011011000010110110010110001011010011100001110010010111010101111110100011111111000011100101100000011110010100011111110001111010010010100101100101010111100100011011100100111010111000111001100110011110011011100011010111000011001010100000101110101000111100010011101111000111011000000100001000000010110011011110101100011011001111110100001111000011101110000101111001000010111010010001011110101101010100000010111110111011110100111011010111110001100011111111010110011001000111011111000100101100111101111000111010011010100000010111011011000010101000001110100111110110010011100101100010101111011001000001111100000111001110100000000011111011110111110110101010110101000000011101111101101";
    elsif rising_edge(clock) then
        if (reg_internal(0) = '1') then
            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10000000000001100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
        else
            reg_internal <= shift_right(reg_internal, 1);
        end if;
    end if;
end process LFSR_2048_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;