Subversion Repositories myhdl_lfsr

-- File: generated/lfsr_4096.vhd
-- Generated by MyHDL 0.9.0
-- Date: Thu Jan 11 17:29:05 2018
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
 
use work.pck_myhdl_090.all;
 
entity lfsr_4096 is
    port (
        reset: in std_logic;
        clock: in std_logic;
        lfsr_out: out unsigned(4095 downto 0)
    );
end entity lfsr_4096;
 
 
architecture MyHDL of lfsr_4096 is
 
 
 
 
 
signal reg_internal: unsigned(4095 downto 0);
 
begin
 
 
 
 
 
LFSR_4096_LFSR_LOGIC: process (clock, reset) is
begin
    if (reset = '1') then
        reg_internal <= unsigned'"0011111001011010101111011011000000010011001011010011101110001111110011010011110010111000110110101100101010111000100001111100110011101111100110110011010101010001010111011101100000011101010011100001101011101111111101010011110010011010101100110010010011011010010101011010110001000010000100111010000100100110110100110011110101000101010101100101110100011110001011000111011110001110101110111010100010001001110000001111010001100001001010001111111000110101110010110110010100100100100001001011010110100111001010010010111011000111010011110101000001111011010011100100011110110011000101111001101111000110010011100100110111001110001011111110101000110011011100111111011110110010011011110101010100001100110110111111000000010000100100110000101110111011000011001010101010101000001011001111101001100111000000101001001010011000101111101101100110011100010101000011100100100001111011000101110010100100111011011010000010000010011100111101000101110000101101110000011111010011110100101110001110001100110001110000101110100100000101110001111011100110101100001001100111101010001000010001001010000101111110011101001101010011010101011001010001110010011010111111100111100100110010110011101101110001111111010000101011000011111101000111100111111001101100100000011001110100011010000010101110011000110010010001111001111101100010011001011110111010011001100110011110111011100000000110110010101100111010101100000100110100110000010111111101000010010001110110100101111010000010011101111011010101011001011010010011111101110000101111111110100110111101101001111111001101000110101001110001110010010001100010001101000111110111010101110011101011011110000001011101000110101101010101111010000101100100001100110100001000010011001110001011111001110110101000100110010100010010110001101010101001110111101000011101011010111101111111010100111101100011000011001000110001000000010011011010000000010110110001101001100101000101010101111010000111001010100001001011010001110110010000111110111110000111110100010011100010010011101100100110010111011110101010010010100001001101001111010111010111100101101001101101010110111000101000001000110101101110101101000100010011110000010110001100101101101010001010010011011010110000111010000100111010011010100001010011001010111000110001101111101010000010111010101110010011100011100000110001011010100101111010111011101011100010100100000000011101110111111100110101100100100011001000101000011011100010111111010100100010100010001110011101011101011110000110100011101000001010100001010110110011111101000111011011011010011010111100100101111111110010010001100101011110000111110011110101000011010011001101000100011011100000011110011000110001010101000001101000011000011101101101010110000110010000110011010101001001011000100000010111111000000010011101010111111100001010010100100010110010111101000111011000111001011110110000000011111110110100000001100101111100000110110001100010101000100101011001011000011010010001011000011000100010110010110010100100011011101100010010111110000000000101000101011100000100111011011110110010011000000100010101001001110010000010111110001110001101100000101110001011100111010011010100011101100101110010001010001011001110010011001000010000110110011110100111010101100110001110000011101100001110010010101111010010100100010000110101011100001011010010101010110111001100001100001111010000110101100001001100000000101100111101010000010000010111001101001110100010011000001101010011101111001101100100110011000111110000011000110101100000111011011110100011000111100100110001111111110111100010100101110000010100001000010111010110011011010010111001100110010010101100110111011110010001011110001101100100111001110101010010101001100001100010001111011010011100111111000010111010100111110000010101101100000000000011011111010111001010010010000001100110110001100111111101000100010000100110010011011000110001100010011010110100110011110011000010011000101100100111110111011011000001011000110111011011010010101111101110010001111010000001010110000111101011111110100111100100000110100110011110110101100100001010010100010000100011101101110010101111111011000101001001100011100010011010100000101000000111001001100101110111111000111010";
    elsif rising_edge(clock) then
        if (reg_internal(0) = '1') then
            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1100000000000001000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
        else
            reg_internal <= shift_right(reg_internal, 1);
        end if;
    end if;
end process LFSR_4096_LFSR_LOGIC;
 
 
 
lfsr_out <= reg_internal;
 
end architecture MyHDL;