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// File: generated/lfsr_2048.v // Generated by MyHDL 0.9.0 // Date: Thu Jan 11 17:13:37 2018 `timescale 1ns/10ps module lfsr_2048 ( reset, clock, out ); input reset; input clock; output [2047:0] out; wire [2047:0] out; reg [2047:0] reg_internal; always @(posedge clock, posedge reset) begin: LFSR_2048_LFSR_LOGIC if (reset == 1) begin reg_internal <= 4246303789197548419185331987884540241389690098851414570675662745781788376768218864091557228342545852312810921124374667816852071497415220662108940562606332129909088463132885617274827012666521923582589600019829203454982095316269005018840235561887595280821654943773127825444913399239780432860703411839276679845735014013595924414195661025803497016865846613457839769104970817763974812015000598779692274272537226680742217527423882241542527888741595525040787476180701937094956572320251336475274772080315091155242806545112268637217216112977577772428192477014418382616962022175213167929655414095213294385845358744036379213820; end else begin if ((reg_internal[0] == 1)) begin reg_internal <= ((reg_internal >>> 1) ^ 2049'h80061000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000); end else begin reg_internal <= (reg_internal >>> 1); end end end assign out = reg_internal; endmodule