Subversion Repositories myhdl_lfsr

// File: generated/lfsr_43.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_43 (
    reset,
    clock,
    out
);
 
 
input reset;
input clock;
output [42:0] out;
wire [42:0] out;
 
reg [42:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_43_LFSR_LOGIC
    if (reset == 1) begin
        reg_internal <= 1744831545637;
    end
    else begin
        if ((reg_internal[0] == 1)) begin
            reg_internal <= ((reg_internal >>> 1) ^ 44'h63000000000);
        end
        else begin
            reg_internal <= (reg_internal >>> 1);
        end
    end
end
 
 
 
assign out = reg_internal;
 
endmodule