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// File: generated/lfsr_513.v // Generated by MyHDL 0.9.0 // Date: Thu Jan 11 17:13:37 2018 `timescale 1ns/10ps module lfsr_513 ( reset, clock, out ); input reset; input clock; output [512:0] out; wire [512:0] out; reg [512:0] reg_internal; always @(posedge clock, posedge reset) begin: LFSR_513_LFSR_LOGIC if (reset == 1) begin reg_internal <= 3083268499313128972540140338587670786118869819889307359452932521473045760757004826593814056464993797010481499347298095949174773122340895422833688772174454; end else begin if ((reg_internal[0] == 1)) begin reg_internal <= ((reg_internal >>> 1) ^ 513'h100000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000); end else begin reg_internal <= (reg_internal >>> 1); end end end assign out = reg_internal; endmodule