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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [tb_lfsr_8.v] - Rev 2
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module tb_lfsr_8; reg reset; reg clock; wire [7:0] out; initial begin $from_myhdl( reset, clock ); $to_myhdl( out ); end lfsr_8 dut( reset, clock, out ); endmodule