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//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application	    : MIG
//  /   /        Filename	    : ddr_fifo_0_wr_en_0.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module generate the write enable signal to the fifos,
//		  which are driven by negedge data strobe.
//*****************************************************************************
 
`timescale 1ns/100ps
module ddr_fifo_0_wr_en_0
  (
   input     clk,
   input     reset,
   input     din,
   output    rst_dqs_delay_n,
   output    dout
   );
 
   localparam TIE_HIGH = 1'b1;
 
   wire      din_delay;
 
   assign rst_dqs_delay_n = ~din_delay;
   assign dout = (din | (din_delay));
 
 
   FDCE delay_ff 
     (.Q  (din_delay), 
      .C  (clk), 
      .CE (TIE_HIGH), 
      .CLR  (reset), 
      .D  (din));
 
endmodule