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<!-- BODY --><b><font size=+2 face="Helvetica, Arial"
color=#bf0000>Project Name: </font></b>
<p><b><font size=+2 face="Helvetica, Arial"
color=#bf0000>OPENCORES Application Board 1 (OAB1)</font></b></p>
<h1><font size="4">Introduction</font></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">As
you know, we have lots of free IP cores here, and we’ll have more coming soon.
We have to use these cores otherwise they are invaluable. For this reason the
idea of designing serials and open design boards are going to be available for
any designers around the world. <o:p>
</o:p>
</span></p>
<h1><span style="mso-bidi-font-size: 12.0pt"><font size="4">Objective<o:p>
</o:p>
</font></span></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
project is intended to: <o:p>
</o:p>
</span></p>
<ul>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
design schematic can deal with analog signal and transport through Ethernet.
<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
implementation CPU core and Ethernet core to one FPGA chip <o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
program the necessary operation system and application software to achieve
the goal.<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
build the prototype board.<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
do the test for all functions.<o:p>
</o:p>
</span></li>
</ul>
<h1><font size="4"><span style="font-family: Arial; mso-bidi-font-size: 12.0pt"> </span>Design
Flow</font></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
project can be divided into two parts. The board design and the cores design.
Anyone can use free or commercial tools to design and implement this project</span></p>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Board
design flow can be done through four steps: <o:p>
</o:p>
</span></p>
<ul>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Block
Diagram design: I hope we use word 97+ for easy modify and exchange. <o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Schematic
entry: I will post schematic using PDF format. Anyone can also send me using
PDF, protel99se or Cadence format. <o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Layout
design: The final layout will use Allegro or Protel99se. <o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Board
implementation: This is the final step in the design where the designer
should work himself to produce his board unless we get funding or donation
from PCB manufactory.<o:p>
</o:p>
</span></li>
</ul>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Cores
design flow can be done through five steps: <o:p>
</o:p>
</span></p>
<ul>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Design
entry: Doesn’t matter the tools, we exchange only VHDL or Verilog codes. <o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Simulation:
I hope to use ModelSim or Active-HDL, but other tools also welcome.<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Synthesis:
I hope to use FPGA express, but other tools also welcome.<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Implementation:
I hope to use Xilinx FPGA.<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Programming
Download: Using onboard parallel cable.<o:p>
</o:p>
</span></li>
</ul>
<h1><font size="4"><span style="font-family: Arial; mso-bidi-font-size: 12.0pt"> </span>System
Description</font></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
is the Board block diagram<br style="mso-special-character: line-break">
<br style="mso-special-character: line-break">
</span><span style="FONT-FAMILY: Verdana"><o:p>
</o:p>
</span><span style="FONT-FAMILY: Verdana"><o:p>
<img border="0" src="ver02.jpg" width="750" height="675"></o:p>
</span></p>
<p class="MsoNormal"><span style="FONT-FAMILY: Verdana"><span style="mso-spacerun: yes">
</span>
</span><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">The
system is composed of 5 main blocks:<o:p>
</o:p>
</span></p>
<ul>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Xilinx
FPGA, PROM and parallel interface<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">SRAM
circuit<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">ADC
and DAC interface<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Ethernet
interface<o:p>
</o:p>
</span></li>
<li>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Power
and reset circuit<o:p>
</o:p>
</span></li>
</ul>
<h1><font size="4">Schematic Design</font></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">TBD<o:p>
</o:p>
</span></p>
<h1><font size="4">Layout Design</font></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">TBD
<o:p>
</o:p>
</span></p>
<h1><font size="4">Current Status:</font></h1>
<p style="mso-margin-top-alt: auto; mso-margin-bottom-alt: auto"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">2001.8.20
Upload Board block diagram <a href="ver01.JPG">version 0.1</a></span></p>
<p style="mso-margin-top-alt: auto; mso-margin-bottom-alt: auto"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">2001.8.21
Upload Board block diagram <a href="ver02.jpg">version 0.2</a></span></p>
<h1><font size="4">Maintainer(s):</font></h1>
<h1><font size="3">Martin Jiang <a href="mailto:martinj@opencores.org"><span style="FONT-FAMILY: 'Times New Roman'; mso-bidi-font-family: Arial">martinj@opencores.org</span></a></font></h1>
<h1><font size="4">Mailing-list:</font></h1>
<p class="MsoNormal"><span style="FONT-FAMILY: Verdana"><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a><o:p>
</o:p>
</span></p>
<h1><font size="4">References tools and links</font></h1>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt"><a href="http://xoscope.sourceforge.net/"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Xscope
home page</span></a> <o:p>
</o:p>
</span></p>
<p class="MsoNormal"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">SSM2141
<a href="http://products.analog.com/products/info.asp?product=SSM2141">Datasheet</a></span></p>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">DAC8248
<a href="http://products.analog.com/products/info.asp?product=DAC8248">Datasheet</a>
</span></p>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">AD7854
<a href="http://products.analog.com/products/info.asp?product=AD7854">Datasheet</a>
</span></p>
<p class="MsoNormal"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">RTL8201</span><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">
<a href="http://www.realtek.com.tw/htm/download/cgi/DLd1.cgi?model=rtl8201&type=1"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Datasheet</span></a><o:p></o:p>
</span></p>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">PE68515
<a href="http://www.pulseeng.com/pdf/H303.pdf">Datasheet</a>
</span></p>
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Xilinx
Virtex-E <a href="http://www.xilinx.com/partinfo/ds022.htm"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Datasheet</span></a><o:p>
</o:p>
</span></p>
<p>
<font size=+1><b>Acknowledgment</b></font>
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