Subversion Repositories opb_wb_wrapper

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##
## Copyright (C) 2000-2004 ASICS World Services, LTD.
##                         www.asics.ws
##                         info@asics.ws
##
##  Author: Rudolf Usselmann
##          rudi@asics.ws
##
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BEGIN opb2wb

## Peripheral Options
OPTION IPTYPE = BRIDGE
OPTION IMP_NETLIST = TRUE
OPTION CORE_STATE = ACTIVE
OPTION STYLE = MIX
OPTION HDL = VERILOG

## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x80000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = BASE, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0x800000ff, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH

# Shared Signals
PORT OPB_Clk     = "",          DIR = IN,  SIGIS = CLK, BUS = SOPB
PORT SYS_Rst     = OPB_Rst,     DIR = IN,  SIGIS = RST, BUS = SOPB

# Ports OPB Slave Attachment
PORT opb_abus    = OPB_ABus,    DIR = IN,  VEC = [0:31], BUS = SOPB
PORT opb_be      = OPB_BE,      DIR = IN,  VEC = [0:3], BUS = SOPB
PORT opb_dbus    = OPB_DBus,    DIR = IN,  VEC = [0:31], BUS = SOPB
PORT opb_rnw     = OPB_RNW,     DIR = IN,  BUS = SOPB
PORT opb_select  = OPB_select,  DIR = IN,  BUS = SOPB
PORT opb_seqaddr = OPB_seqAddr, DIR = IN,  BUS = SOPB
PORT sl_dbus     = Sl_DBus,     DIR = OUT, VEC = [0:31], BUS = SOPB
PORT sl_errack   = Sl_errAck,   DIR = OUT, BUS = SOPB
PORT sl_retry    = Sl_retry,    DIR = OUT, BUS = SOPB
PORT sl_toutsup  = Sl_toutSup,  DIR = OUT, BUS = SOPB
PORT sl_xferack  = Sl_xferAck,  DIR = OUT, BUS = SOPB

# WISHBONE Master Interface
PORT wb_data_o = "", DIR = OUT, VEC = [31:0]
PORT wb_data_i = "", DIR = IN,  VEC = [31:0]
PORT wb_addr_o = "", DIR = OUT, VEC = [31:0]
PORT wb_cyc_o  = "", DIR = OUT
PORT wb_stb_o  = "", DIR = OUT
PORT wb_sel_o  = "", DIR = OUT, VEC = [3:0]
PORT wb_we_o   = "", DIR = OUT
PORT wb_ack_i  = "", DIR = IN
PORT wb_err_i  = "", DIR = IN
PORT wb_rty_i  = "", DIR = IN

END