Subversion Repositories opb_wb_wrapper

################################################################################
##
## Copyright (C) 2000-2004 ASICS World Services, LTD.
##                         www.asics.ws
##                         info@asics.ws
##
##  Author: Rudolf Usselmann
##          rudi@asics.ws
##
################################################################################

BEGIN wb2opb

## Peripheral Options
OPTION IPTYPE = BRIDGE
OPTION IMP_NETLIST = TRUE
OPTION CORE_STATE = ACTIVE
OPTION STYLE = MIX
OPTION HDL = VERILOG

## Bus Interfaces
BUS_INTERFACE BUS = MOPB, BUS_STD = OPB, BUS_TYPE = MASTER

## Shared Signals
PORT OPB_Clk     = "",          DIR = IN, SIGIS = CLK, BUS = MOPB
PORT rst         = OPB_Rst,             DIR = IN, BUS = MOPB

## Ports OPB Master Attachment
PORT opb_abus    = M_ABus,      DIR = OUT, VEC = [0:31], BUS = MOPB
PORT opb_be      = M_BE,        DIR = OUT, VEC = [0:3], BUS = MOPB
PORT opb_dbus    = M_DBus,      DIR = OUT, VEC = [0:31], BUS = MOPB
PORT opb_rnw     = M_RNW,       DIR = OUT, BUS = MOPB
PORT opb_select  = M_select,    DIR = OUT, BUS = MOPB
PORT opb_seqaddr = M_seqAddr,   DIR = OUT, BUS = MOPB
PORT sl_dbus     = OPB_DBus,    DIR = IN, VEC = [0:31], BUS = MOPB
PORT sl_errack   = OPB_errAck,  DIR = IN, BUS = MOPB
PORT sl_retry    = OPB_retry,   DIR = IN, BUS = MOPB
PORT sl_xferack  = OPB_xferAck, DIR = IN, BUS = MOPB
PORT opb_req     = M_request,   DIR = OUT, BUS = MOPB
PORT opb_gnt     = OPB_MGrant,  DIR = IN, BUS = MOPB
PORT opb_buslock = M_busLock,   DIR = OUT, BUS = MOPB

## WISHBONE Slave Interface
PORT wb_data_o = "", DIR = OUT, VEC = [31:0]
PORT wb_data_i = "", DIR = IN, VEC = [31:0]
PORT wb_addr_i = "", DIR = IN, VEC = [31:0]
PORT wb_cyc_i  = "", DIR = IN
PORT wb_stb_i  = "", DIR = IN
PORT wb_sel_i  = "", DIR = IN, VEC = [3:0]
PORT wb_we_i   = "", DIR = IN
PORT wb_ack_o  = "", DIR = OUT
PORT wb_err_o  = "", DIR = OUT
PORT wb_rty_o  = "", DIR = OUT

END