OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [taskmgr/] [sys_hw_map.s] - Rev 301

Compare with Previous | Blame | View Log

; Copyright (c)2022 Jeremy Seth Henry
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Redistributions in binary form must reproduce the above copyright
;       notice, this list of conditions and the following disclaimer in the
;       documentation and/or other materials provided with the distribution,
;       where applicable (as part of a user interface, debugging port, etc.)
;
; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;------------------------------------------------------------------------------
; sys_hw_map.s
;
; Defines the interface between HDL and assembly, and should be derived from
;  Open8_cfg.vhd (this is a minimal configuration)
;
; Revision History
; Author          Date     Change
;---------------- -------- ---------------------------------------------------
; Seth Henry      7/15/22  Initial Release
;------------------------------------------------------------------------------
 
;------------------------------------------------------------------------------
; System Memory Map from Open8_cfg
;------------------------------------------------------------------------------
.DEFINE RAM_Address          $0000 ; System RAM
.DEFINE WPR_Address          $1000 ; RAM Write Protect Mask
.DEFINE WQL_Address          $1020 ; I/O Write Qual Register
.DEFINE INT_Address          $1040 ; Cascaded Interrupt Manager
;...
.DEFINE ROM_Address          $8000 ; Application ROM
.DEFINE ISR_Start_Addr       $FFF0 ; ISR vector table
;------------------------------------------------------------------------------
 
;------------------------------------------------------------------------------
; Interrupt Manager Selection
;
; Uncomment the INTMGR16 define if using the 16-bit "complex" interrupt manager
;  firmware. Otherwise, the 8-bit "simple" external interrupt manager is
;  assumed. Note that the interfaces are NOT register compatible, so this will
;  break the system if the wrong manager is selected!
;
;.DEFINE INTMGR16
;------------------------------------------------------------------------------
 
;------------------------------------------------------------------------------
; RAM Configuration
;------------------------------------------------------------------------------
; Define the size of the memory and number of partitions in order to configure
;  the region size constant - which will be used by tasks to assign their
;  write-protection requirements
.DEFINE RAM_Size             4096
.DEFINE RAM_Partitions       32
;------------------------------------------------------------------------------
 
;------------------------------------------------------------------------------
; Write Qualification Groups from Open8_cfg
;------------------------------------------------------------------------------
 
;------------------------------------------------------------------------------

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.