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////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	fasttop.v
//
// Project:	OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose:	This is the top level Verilog file.  It is so named as fasttop,
//		because my purpose will be to run the Arty at 200MHz, just to
//	prove that I can get it up to that frequency.
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module fasttop(i_clk_100mhz, i_reset_btn,
	i_sw,			// Switches
	i_btn,			// Buttons
	o_led,			// Single color LEDs
	o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,	// Color LEDs
	// RS232 UART
	i_uart_rx, o_uart_tx,
	// Quad-SPI Flash control
	o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
	// Missing: Ethernet
	o_eth_mdclk, io_eth_mdio,
	// Memory
	o_ddr_reset_n, o_ddr_cke, o_ddr_ck_p, o_ddr_ck_n,
	o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
	io_ddr_dqs_p, io_ddr_dqs_n,
	o_ddr_addr, o_ddr_ba,
	io_ddr_data, o_ddr_dm, o_ddr_odt,
	// SD Card
	o_sd_sck, io_sd_cmd, io_sd, i_sd_cs, i_sd_wp,
	// GPS Pmod
	i_gps_pps, i_gps_3df, i_gps_rx, o_gps_tx,
	// OLED Pmod
	o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n,
		o_oled_vccen, o_oled_pmoden,
	// PMod I/O
	i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts
	);
	input			i_clk_100mhz, i_reset_btn;
	input		[3:0]	i_sw;	// Switches
	input		[3:0]	i_btn;	// Buttons
	output	wire	[3:0]	o_led;	// LED
	output	wire	[2:0]	o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
	// UARTs
	input			i_uart_rx;
	output	wire		o_uart_tx;
	// Quad SPI flash
	output	wire		o_qspi_sck, o_qspi_cs_n;
	inout	[3:0]		io_qspi_dat;
	// Ethernet // Not yet implemented
	// Ethernet control (MDIO)
	output	wire		o_eth_mdclk;
	inout	wire		io_eth_mdio;
	// DDR3 SDRAM
	output	wire		o_ddr_reset_n;
	output	wire		o_ddr_cke;
	output	wire		o_ddr_ck_p, o_ddr_ck_n;
	output	wire		o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
	inout		[1:0]	io_ddr_dqs_p, io_ddr_dqs_n;
	output	wire	[13:0]	o_ddr_addr;
	output	wire	[2:0]	o_ddr_ba;
	inout		[15:0]	io_ddr_data;
	//
	output	wire	[1:0]	o_ddr_dm;
	output	wire		o_ddr_odt;
	// SD Card
	output	wire		o_sd_sck;
	inout			io_sd_cmd;
	inout		[3:0]	io_sd;
	input			i_sd_cs;
	input			i_sd_wp;
	// GPS PMod
	input			i_gps_pps, i_gps_3df, i_gps_rx;
	output	wire		o_gps_tx;
	// OLEDRGB PMod
	output	wire		o_oled_sck, o_oled_cs_n, o_oled_mosi,
				o_oled_dcn, o_oled_reset_n, o_oled_vccen,
				o_oled_pmoden;
	// Aux UART
	input			i_aux_rx, i_aux_rts;
	output	wire		o_aux_tx, o_aux_cts;
 
`define	FULLCLOCK
	// Build our master clock
	wire	i_clk, clk_for_ddr, clk2_unused, enet_clk, clk_analyzer,
		clk_feedback, clk_locked, clk_analyzer_b;
	PLLE2_BASE	#(
		.BANDWIDTH("OPTIMIZED"),	// OPTIMIZED, HIGH, LOW
		.CLKFBOUT_PHASE(0.0),	// Phase offset in degrees of CLKFB, (-360-360)
		.CLKIN1_PERIOD(10.0),	// Input clock period in ns to ps resolution
`ifdef	FULLCLOCK
		// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
		.CLKFBOUT_MULT(8),	// Multiply value for all CLKOUT (2-64)
		.CLKOUT0_DIVIDE(4),	// 200 MHz
		.CLKOUT1_DIVIDE(4),	// 200 MHz clock for DDR memory
		.CLKOUT2_DIVIDE(8),	// 100 MHz
		.CLKOUT3_DIVIDE(32),	//  25 MHz
		.CLKOUT4_DIVIDE(1),	// 800 MHz
		.CLKOUT5_DIVIDE(1),
`else
		// 100*64/40 = 160 -- the fastest speed where the UART will 
		// still work at 4MBaud.  Others will still support 115200
		// Baud
		// 100*64/36 = 177.78
		// 100*64/34 = 188.24
		// 100*64/33 = 193.94
		.CLKFBOUT_MULT(8),	// Multiply value for all CLKOUT (2-64)
		.CLKOUT0_DIVIDE(5),	// 160 MHz
		.CLKOUT1_DIVIDE(5),	// 160 MHz //Clock too slow for DDR mem
		.CLKOUT2_DIVIDE(10),	//  80 MHz
		.CLKOUT3_DIVIDE(40),	//  20 MHz
		.CLKOUT4_DIVIDE(1),	//  40 MHz
		.CLKOUT5_DIVIDE(1),
`endif
		// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
		.CLKOUT0_DUTY_CYCLE(0.5),
		.CLKOUT1_DUTY_CYCLE(0.5),
		.CLKOUT2_DUTY_CYCLE(0.5),
		.CLKOUT3_DUTY_CYCLE(0.5),
		.CLKOUT4_DUTY_CYCLE(0.5),
		.CLKOUT5_DUTY_CYCLE(0.5),
		// CLKOUT0_PHASE -- phase offset for each CLKOUT
		.CLKOUT0_PHASE(0.0),
		.CLKOUT1_PHASE(270.0),
		.CLKOUT2_PHASE(0.0),
		.CLKOUT3_PHASE(0.0),
		.CLKOUT4_PHASE(0.0),
		.CLKOUT5_PHASE(180.0),
		.DIVCLK_DIVIDE(1),	// Master division value , (1-56)
		.REF_JITTER1(0.0),	// Reference input jitter in UI (0.000-0.999)
		.STARTUP_WAIT("FALSE")	// Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
	) genclock(
		// Clock outputs: 1-bit (each) output
		.CLKOUT0(i_clk),
		.CLKOUT1(clk_for_ddr),
		.CLKOUT2(clk2_unused), // Reserved for flash, should we need it
		.CLKOUT3(enet_clk),
		.CLKOUT4(clk_analyzer),
		.CLKOUT5(clk_analyzer_b),
		.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
		.LOCKED(clk_locked),
		.CLKIN1(i_clk_100mhz),
		.PWRDWN(1'b0),
		.RST(1'b0),
		.CLKFBIN(clk_feedback)	// 1-bit input, feedback clock
	);
 
	// UART interface
	wire	[29:0]	bus_uart_setup;
`ifdef	FULLCLOCK
	assign		bus_uart_setup = 30'h10000032; // 4MBaud, 7 bits
`else
	assign		bus_uart_setup = 30'h10000028;//4MBaud,7 bits,@160MHzClk
	//assign	bus_uart_setup = 30'h10000019;//4MBaud,7 bits,@100MHzClk
`endif
 
	wire	[7:0]	rx_data, tx_data;
	wire		rx_break, rx_parity_err, rx_frame_err, rx_stb;
	wire		tx_stb, tx_busy;
 
	reg	pwr_reset, pre_reset;
	initial	pwr_reset = 1'b1;
	initial	pre_reset = 1'b0;
	always @(posedge i_clk)
		pre_reset <= ~i_reset_btn;
	always @(posedge i_clk)
		pwr_reset <= pre_reset;
 
	wire	w_ck_uart, w_uart_tx;
	rxuart	rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
				rx_stb, rx_data, rx_break,
				rx_parity_err, rx_frame_err, w_ck_uart);
	txuart	txv(i_clk, pwr_reset, bus_uart_setup, 1'b0,
				tx_stb, tx_data, o_uart_tx, tx_busy);
 
 
 
 
 
 
	//////
	//
	//
	// The WB bus interconnect, herein called fastmaster, which handles
	// just about ... everything.
	//
	//
	//////
	wire		w_qspi_sck, w_qspi_cs_n;
	wire	[1:0]	qspi_bmod;
	wire	[3:0]	qspi_dat;
	wire	[3:0]	i_qspi_dat;
 
	//
	wire	[31:0]	wo_ddr_data, wi_ddr_data;
	wire		w_ddr_dqs, w_ddr_dm, w_ddr_bus_oe, w_ddr_odt;
	wire	[2:0]	w_ddr_ba;
	wire		w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n;
	wire	[13:0]	w_ddr_addr;
	reg	[31:0]	r_ddr_data;
 
	//
	wire		w_mdio, w_mdwe;
	//
	wire		w_sd_cmd;
	wire	[3:0]	w_sd_data;
	fastmaster	wbbus(i_clk, pwr_reset,
		// External USB-UART bus control
		rx_stb, rx_data, tx_stb, tx_data, tx_busy,
		// Board lights and switches
		i_sw, i_btn, o_led,
		o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
		// Board level PMod I/O
		i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
		// Quad SPI flash
		w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
		// DDR3 SDRAM
		o_ddr_reset_n, o_ddr_cke,
		w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n,
		w_ddr_dqs, w_ddr_dm, w_ddr_odt, w_ddr_bus_oe,
		w_ddr_addr, w_ddr_ba, wo_ddr_data, r_ddr_data,
		// SD Card
		o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
		// Ethernet control (MDIO) lines
		o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
		// OLEDRGB PMod wires
		o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
		o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
		// GPS PMod
		i_gps_pps, i_gps_3df
		);
 
	//////
	//
	//
	// Some wires need special treatment, and so are not quite completely
	// handled by the bus master.  These are handled below.
	//
	//
	//////
 
	//
	//
	// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
	//	0?	Normal serial mode, one bit in one bit out
	//	10	Quad SPI mode, going out
	//	11	Quad SPI mode coming from the device (read mode)
	//
	//	??	Dual mode in  (not yet)
	//	??	Dual mode out (not yet)
	//
	//
// `define	QSPI_OUT_VERSION_ONE
`ifdef	QSPI_OUT_VERSION_ONE
	assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
				:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
	assign	i_qspi_dat = io_qspi_dat;
	assign	o_qspi_sck = w_qspi_sck;
`else
	wire	[3:0]	i_qspi_pedge, i_qspi_nedge;
 
	xoddr	xqspi_sck( i_clk, { w_qspi_sck,  w_qspi_sck }, o_qspi_sck);
	xoddr	xqspi_csn( i_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
	//
	xioddr	xqspi_d0(  i_clk, (qspi_bmod != 2'b11),
		{ qspi_dat[0], qspi_dat[0] },
		{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
	xioddr	xqspi_d1(  i_clk, (qspi_bmod==2'b10),
		{ qspi_dat[1], qspi_dat[1] },
		{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
	xioddr	xqspi_d2(  i_clk, (qspi_bmod!=2'b11),
		(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
		{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
	xioddr	xqspi_d3(  i_clk, (qspi_bmod!=2'b11),
		(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
		{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
 
	assign	i_qspi_dat = i_qspi_pedge;
`endif
 
	//
	//
	// Wires for setting up the SD Card Controller
	//
	//
	assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
	assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
	assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
	assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
	assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
 
 
	//
	//
	// Wire(s) for setting up the MDIO ethernet control structure
	//
	//
	assign	io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
 
	//
	//
	// Wires for setting up the DDR3 memory
	//
	//
`ifdef	SDRAM_ACCESS
	reg	[15:0]	bottom_half_data;
	always @(posedge i_clk)
		bottom_half_data <= wo_ddr_data[15:0];
	xioddr	p0(i_clk, w_ddr_bus_oe, { wo_ddr_data[16], wo_ddr_data[0] },
		{ wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
 
	xioddr	p1(i_clk, w_ddr_bus_oe, { wo_ddr_data[17], wo_ddr_data[1] },
		{ wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
 
	xioddr	p2(i_clk, w_ddr_bus_oe, { wo_ddr_data[18], wo_ddr_data[2] },
		{ wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
 
	xioddr	p3(i_clk, w_ddr_bus_oe, { wo_ddr_data[19], wo_ddr_data[3] },
		{ wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
 
	xioddr	p4(i_clk, w_ddr_bus_oe, { wo_ddr_data[20], wo_ddr_data[4] },
		{ wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
 
	xioddr	p5(i_clk, w_ddr_bus_oe, { wo_ddr_data[21], wo_ddr_data[5] },
		{ wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
 
	xioddr	p6(i_clk, w_ddr_bus_oe, { wo_ddr_data[22], wo_ddr_data[6] },
		{ wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
 
	xioddr	p7(i_clk, w_ddr_bus_oe, { wo_ddr_data[23], wo_ddr_data[7] },
		{ wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
 
	xioddr	p8(i_clk, w_ddr_bus_oe, { wo_ddr_data[24], wo_ddr_data[8] },
		{ wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
 
	xioddr	p9(i_clk, w_ddr_bus_oe, { wo_ddr_data[25], wo_ddr_data[9] },
		{ wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
 
	xioddr	pa(i_clk, w_ddr_bus_oe, { wo_ddr_data[26], wo_ddr_data[10] },
		{ wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
 
	xioddr	pb(i_clk, w_ddr_bus_oe, { wo_ddr_data[27], wo_ddr_data[11] },
		{ wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
 
	xioddr	pc(i_clk, w_ddr_bus_oe, { wo_ddr_data[28], wo_ddr_data[12] },
		{ wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
 
	xioddr	pd(i_clk, w_ddr_bus_oe, { wo_ddr_data[29], wo_ddr_data[13] },
		{ wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
 
	xioddr	pe(i_clk, w_ddr_bus_oe, { wo_ddr_data[30], wo_ddr_data[14] },
		{ wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
 
	xioddr	pf(i_clk, w_ddr_bus_oe, { wo_ddr_data[31], wo_ddr_data[15] },
		{ wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
	always @(posedge i_clk)
		r_ddr_data <= wi_ddr_data;
 
	wire	[7:0]	w_dqs_ignore;
	xioddrds	dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
		{ w_dqs_ignore[0], w_dqs_ignore[1] },
		io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
	xioddrds	dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
		{ w_dqs_ignore[2], w_dqs_ignore[3] },
		io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
 
	xoddr	xcs_n( i_clk, { w_ddr_cs_n,  w_ddr_cs_n  }, o_ddr_cs_n);
	xoddr	xras_n(i_clk, { w_ddr_ras_n, w_ddr_ras_n }, o_ddr_ras_n);
	xoddr	xcas_n(i_clk, { w_ddr_cas_n, w_ddr_cas_n }, o_ddr_cas_n);
	xoddr	xwe_n( i_clk, { w_ddr_we_n,  w_ddr_we_n  }, o_ddr_we_n);
	xoddr	xba0(  i_clk, { w_ddr_ba[0], w_ddr_ba[0]  }, o_ddr_ba[0]);
	xoddr	xba1(  i_clk, { w_ddr_ba[1], w_ddr_ba[1]  }, o_ddr_ba[1]);
	xoddr	xba2(  i_clk, { w_ddr_ba[2], w_ddr_ba[2]  }, o_ddr_ba[2]);
	xoddr	xaddr0(i_clk, { w_ddr_addr[0], w_ddr_addr[0] }, o_ddr_addr[0]);
	xoddr	xaddr1(i_clk, { w_ddr_addr[1], w_ddr_addr[1] }, o_ddr_addr[1]);
	xoddr	xaddr2(i_clk, { w_ddr_addr[2], w_ddr_addr[2] }, o_ddr_addr[2]);
	xoddr	xaddr3(i_clk, { w_ddr_addr[3], w_ddr_addr[3] }, o_ddr_addr[3]);
	xoddr	xaddr4(i_clk, { w_ddr_addr[4], w_ddr_addr[4] }, o_ddr_addr[4]);
	xoddr	xaddr5(i_clk, { w_ddr_addr[5], w_ddr_addr[5] }, o_ddr_addr[5]);
	xoddr	xaddr6(i_clk, { w_ddr_addr[6], w_ddr_addr[6] }, o_ddr_addr[6]);
	xoddr	xaddr7(i_clk, { w_ddr_addr[7], w_ddr_addr[7] }, o_ddr_addr[7]);
	xoddr	xaddr8(i_clk, { w_ddr_addr[8], w_ddr_addr[8] }, o_ddr_addr[8]);
	xoddr	xaddr9(i_clk, { w_ddr_addr[9], w_ddr_addr[9] }, o_ddr_addr[9]);
	xoddr	xaddr10(i_clk,{ w_ddr_addr[10],w_ddr_addr[10]}, o_ddr_addr[10]);
	xoddr	xaddr11(i_clk,{ w_ddr_addr[11],w_ddr_addr[11]}, o_ddr_addr[11]);
	xoddr	xaddr12(i_clk,{ w_ddr_addr[12],w_ddr_addr[12]}, o_ddr_addr[12]);
	xoddr	xaddr13(i_clk,{ w_ddr_addr[13],w_ddr_addr[13]}, o_ddr_addr[13]);
 
	wire	w_clk_for_ddr;
	ODDR	#(.DDR_CLK_EDGE("SAME_EDGE"))
		memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
			.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
	OBUFDS	#(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
		clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
 
	// assign	o_ddr_dm[0] = w_ddr_dm;
	// assign	o_ddr_dm[1] = w_ddr_dm;
	xoddr	xdm0(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[0]);
	xoddr	xdm1(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[1]);
 
	assign	o_ddr_odt = (~o_ddr_reset_n)? 1'bz : w_ddr_odt;
 
	// xlogicanalyzer ladata(i_clk, io_ddr_data[0], w_ddr_debug[3:0]);
	// xlogicanalyzer ladclk(clk_analyzer, clk_analyzer_b,
		// i_clk, o_ddr_ck_p, w_ddr_debug[7:4]);
	assign w_ddr_debug[7:4] = 4'h0;
	assign w_ddr_debug[3:0] = 4'h0;
`else
	assign	o_ddr_cs_n = w_ddr_cs_n;
	assign	o_ddr_ras_n = w_ddr_ras_n;
	assign	o_ddr_cas_n = w_ddr_cas_n;
	assign	o_ddr_we_n = w_ddr_we_n;
	//
	assign	o_ddr_ba = w_ddr_ba;
	assign	o_ddr_addr = w_ddr_addr;
	//
	assign	o_ddr_dm[1:0] = 2'b00;
	assign	o_ddr_odt     = 1'b0;
	//
	assign	io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
	always @(posedge i_clk)
		r_ddr_data = 16'h0000;
 
	//wire	w_clk_for_ddr;
	//ODDR	#(.DDR_CLK_EDGE("SAME_EDGE"))
		//memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
			//.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
	OBUFDS	#(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
		clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(1'b1));
 
	wire	[7:0]	w_dqs_ignore;
	xioddrds	dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
		{ w_dqs_ignore[0], w_dqs_ignore[1] },
		io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
	xioddrds	dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
		{ w_dqs_ignore[2], w_dqs_ignore[3] },
		io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
 
 
`endif
 
endmodule