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[/] [openjtag-project/] [trunk/] [OpenJTAG/] [Quartus_II/] [Open_JTAG.fit.rpt] - Rev 18
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Fitter report for Open_JTAGWed Jun 02 16:01:11 2010Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Pin-Out File6. Fitter Resource Usage Summary7. Input Pins8. Output Pins9. Bidir Pins10. I/O Bank Usage11. All Package Pins12. Output Pin Default Load For Reported TCO13. Fitter Resource Utilization by Entity14. Delay Chain Summary15. Control Signals16. Global & Other Fast Signals17. Non-Global High Fan-Out Signals18. Interconnect Usage Summary19. LAB Logic Elements20. LAB-wide Signals21. LAB Signals Sourced22. LAB Signals Sourced Out23. LAB Distinct Inputs24. Fitter Device Options25. Estimated Delay Added for Hold Timing26. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+----------------------------------------------------------------------+; Fitter Summary ;+-----------------------+----------------------------------------------+; Fitter Status ; Successful - Wed Jun 02 16:01:11 2010 ;; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;; Revision Name ; Open_JTAG ;; Top-level Entity Name ; Open_JTAG ;; Family ; MAX II ;; Device ; EPM570T100C5 ;; Timing Models ; Final ;; Total logic elements ; 245 / 570 ( 43 % ) ;; Total pins ; 29 / 76 ( 38 % ) ;; Total virtual pins ; 0 ;; UFM blocks ; 0 / 1 ( 0 % ) ;+-----------------------+----------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; EPM570T100C5 ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Use TimeQuest Timing Analyzer ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Multi-Corner Timing ; Off ; Off ;; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate full fit report during ECO compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; Slow Slew Rate ; Off ; Off ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Delay Chains ; On ; On ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;; Auto Register Duplication ; Auto ; Auto ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Stop After Congestion Map Generation ; Off ; Off ;; Save Intermediate Fitting Results ; Off ; Off ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;; Use Best Effort Settings for Compilation ; Off ; Off ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 4 ;; Maximum allowed ; 1 ;+----------------------------+--------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in C:/AlteraWorks/91/Open JTAG/Open_JTAG.pin.+-----------------------------------------------------------------------+; Fitter Resource Usage Summary ;+---------------------------------------------+-------------------------+; Resource ; Usage ;+---------------------------------------------+-------------------------+; Total logic elements ; 245 / 570 ( 43 % ) ;; -- Combinational with no register ; 157 ;; -- Register only ; 20 ;; -- Combinational with a register ; 68 ;; ; ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 134 ;; -- 3 input functions ; 50 ;; -- 2 input functions ; 30 ;; -- 1 input functions ; 11 ;; -- 0 input functions ; 0 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 237 ;; -- arithmetic mode ; 8 ;; -- qfbk mode ; 12 ;; -- register cascade mode ; 0 ;; -- synchronous clear/load mode ; 23 ;; -- asynchronous clear/load mode ; 1 ;; ; ;; Total registers ; 88 / 570 ( 15 % ) ;; Total LABs ; 28 / 57 ( 49 % ) ;; Logic elements in carry chains ; 10 ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 29 / 76 ( 38 % ) ;; -- Clock pins ; 3 / 4 ( 75 % ) ;; Global signals ; 2 ;; UFM blocks ; 0 / 1 ( 0 % ) ;; Global clocks ; 2 / 4 ( 50 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 20% / 24% / 15% ;; Peak interconnect usage (total/H/V) ; 20% / 24% / 15% ;; Maximum fan-out node ; clock_mux:inst1|wcks ;; Maximum fan-out ; 75 ;; Highest non-global fan-out signal ; serializer:inst2|ssm[3] ;; Highest non-global fan-out ; 34 ;; Total fan-out ; 962 ;; Average fan-out ; 3.51 ;+---------------------------------------------+-------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+; clk ; 12 ; 1 ; 0 ; 5 ; 0 ; 14 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;; rst ; 73 ; 2 ; 13 ; 7 ; 5 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;; rxf ; 71 ; 2 ; 13 ; 6 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;; tdo ; 91 ; 2 ; 6 ; 8 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;; txe ; 38 ; 1 ; 7 ; 3 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ;+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+--------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;+--------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+; new_state[0] ; 5 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ;; new_state[1] ; 29 ; 1 ; 4 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; new_state[2] ; 33 ; 1 ; 6 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; new_state[3] ; 8 ; 1 ; 0 ; 7 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; rd ; 3 ; 1 ; 1 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; sm[0] ; 17 ; 1 ; 0 ; 5 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; sm[1] ; 30 ; 1 ; 4 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ;; sm[2] ; 43 ; 1 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; sm[3] ; 70 ; 2 ; 13 ; 6 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; tck ; 97 ; 2 ; 5 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; tdi ; 15 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; tms ; 87 ; 2 ; 7 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; trst ; 4 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; wcks ; 44 ; 1 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; wr ; 14 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ;; wrk ; 1 ; 2 ; 3 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ;+--------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Bidir Pins ;+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+---------------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+---------------------------+---------------------+; db[0] ; 64 ; 2 ; 13 ; 4 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[0]~en ; - ;; db[1] ; 41 ; 1 ; 7 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; serializer:inst2|db[1]~en ; - ;; db[2] ; 40 ; 1 ; 7 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; serializer:inst2|db[2]~en ; - ;; db[3] ; 92 ; 2 ; 6 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[3]~en ; - ;; db[4] ; 42 ; 1 ; 7 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[4]~en ; - ;; db[5] ; 36 ; 1 ; 6 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[5]~en ; - ;; db[6] ; 34 ; 1 ; 6 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[6]~en ; - ;; db[7] ; 18 ; 1 ; 0 ; 5 ; 5 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[7]~en ; - ;+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+---------------------------+---------------------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 20 / 36 ( 56 % ) ; 3.3V ; -- ;; 2 ; 9 / 40 ( 23 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+; 1 ; 161 ; 2 ; wrk ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 2 ; 2 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 3 ; 4 ; 1 ; rd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 4 ; 6 ; 1 ; trst ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 5 ; 8 ; 1 ; new_state[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 6 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 7 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 8 ; 11 ; 1 ; new_state[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;; 12 ; 20 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;; 14 ; 21 ; 1 ; wr ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 15 ; 22 ; 1 ; tdi ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 16 ; 23 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 17 ; 24 ; 1 ; sm[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 18 ; 25 ; 1 ; db[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 19 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 20 ; 34 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 21 ; 36 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 22 ; 38 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; 23 ; 39 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; 24 ; 40 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; 25 ; 41 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; 26 ; 47 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 27 ; 48 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 28 ; 50 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 29 ; 51 ; 1 ; new_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 30 ; 52 ; 1 ; sm[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;; 33 ; 58 ; 1 ; new_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 34 ; 59 ; 1 ; db[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 35 ; 60 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 36 ; 61 ; 1 ; db[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 37 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;; 38 ; 62 ; 1 ; txe ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 39 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;; 40 ; 63 ; 1 ; db[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 41 ; 64 ; 1 ; db[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 42 ; 65 ; 1 ; db[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 43 ; 66 ; 1 ; sm[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 44 ; 67 ; 1 ; wcks ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;; 47 ; 71 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 48 ; 72 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 49 ; 73 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 50 ; 75 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 51 ; 79 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 52 ; 83 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 53 ; 84 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 54 ; 86 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 55 ; 89 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 56 ; 91 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 57 ; 92 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 58 ; 93 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;; 61 ; 98 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 62 ; 101 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;; 64 ; 102 ; 2 ; db[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;; 66 ; 103 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 67 ; 104 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 68 ; 105 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 69 ; 111 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 70 ; 112 ; 2 ; sm[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 71 ; 115 ; 2 ; rxf ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 72 ; 116 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 73 ; 118 ; 2 ; rst ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 74 ; 120 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 75 ; 122 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 76 ; 125 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 77 ; 126 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 78 ; 127 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 81 ; 135 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 82 ; 136 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 83 ; 139 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 84 ; 140 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 85 ; 141 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 86 ; 142 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 87 ; 143 ; 2 ; tms ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 88 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;; 89 ; 144 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 90 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;; 91 ; 149 ; 2 ; tdo ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 92 ; 150 ; 2 ; db[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 95 ; 151 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 96 ; 152 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 97 ; 153 ; 2 ; tck ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 98 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 99 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 100 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------+-------+------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------+-------+------------------------+; 3.3-V LVTTL ; 10 pF ; Not Available ;; 3.3-V LVCMOS ; 10 pF ; Not Available ;; 2.5 V ; 10 pF ; Not Available ;; 1.8 V ; 10 pF ; Not Available ;; 1.5 V ; 10 pF ; Not Available ;; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;+----------------------------+-------+------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+; |Open_JTAG ; 245 (1) ; 88 ; 0 ; 29 ; 0 ; 157 (1) ; 20 (0) ; 68 (0) ; 10 (0) ; 12 (1) ; |Open_JTAG ; work ;; |clock_mux:inst1| ; 15 (15) ; 14 ; 0 ; 0 ; 0 ; 1 (1) ; 3 (3) ; 11 (11) ; 6 (6) ; 6 (6) ; |Open_JTAG|clock_mux:inst1 ; work ;; |serializer:inst2| ; 171 (171) ; 58 ; 0 ; 0 ; 0 ; 113 (113) ; 13 (13) ; 45 (45) ; 4 (4) ; 1 (1) ; |Open_JTAG|serializer:inst2 ; work ;; |tap_sm:inst| ; 58 (58) ; 16 ; 0 ; 0 ; 0 ; 42 (42) ; 4 (4) ; 12 (12) ; 0 (0) ; 4 (4) ; |Open_JTAG|tap_sm:inst ; work ;+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-----------------------------------------+; Delay Chain Summary ;+--------------+----------+---------------+; Name ; Pin Type ; Pad to Core 0 ;+--------------+----------+---------------+; rst ; Input ; (0) ;; rxf ; Input ; (1) ;; clk ; Input ; (1) ;; txe ; Input ; (1) ;; tdo ; Input ; (1) ;; tms ; Output ; -- ;; tck ; Output ; -- ;; wrk ; Output ; -- ;; wr ; Output ; -- ;; rd ; Output ; -- ;; tdi ; Output ; -- ;; trst ; Output ; -- ;; wcks ; Output ; -- ;; new_state[3] ; Output ; -- ;; new_state[2] ; Output ; -- ;; new_state[1] ; Output ; -- ;; new_state[0] ; Output ; -- ;; sm[3] ; Output ; -- ;; sm[2] ; Output ; -- ;; sm[1] ; Output ; -- ;; sm[0] ; Output ; -- ;; db[7] ; Bidir ; (1) ;; db[6] ; Bidir ; (1) ;; db[5] ; Bidir ; (1) ;; db[4] ; Bidir ; (1) ;; db[3] ; Bidir ; (1) ;; db[2] ; Bidir ; (1) ;; db[1] ; Bidir ; (1) ;; db[0] ; Bidir ; (1) ;+--------------+----------+---------------++----------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+---------------------------------+-------------+---------+---------------------------+--------+----------------------+------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;+---------------------------------+-------------+---------+---------------------------+--------+----------------------+------------------+; clk ; PIN_12 ; 14 ; Clock ; yes ; Global Clock ; GCLK0 ;; clock_mux:inst1|Equal0~1 ; LC_X7_Y5_N9 ; 14 ; Async. load, Clock enable ; no ; -- ; -- ;; clock_mux:inst1|wcks ; LC_X8_Y5_N5 ; 75 ; Clock ; yes ; Global Clock ; GCLK3 ;; serializer:inst2|cks[0]~0 ; LC_X7_Y5_N4 ; 3 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|count[1]~11 ; LC_X2_Y5_N3 ; 2 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|db[0]~en ; LC_X9_Y4_N1 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[1]~en ; LC_X7_Y4_N0 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[2]~en ; LC_X7_Y4_N9 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[3]~en ; LC_X6_Y5_N4 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[4]~en ; LC_X6_Y5_N5 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[5]~en ; LC_X6_Y5_N9 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[6]~en ; LC_X6_Y5_N6 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|db[7]~8 ; LC_X5_Y4_N0 ; 16 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|db[7]~en ; LC_X6_Y5_N1 ; 1 ; Output enable ; no ; -- ; -- ;; serializer:inst2|instr ; LC_X5_Y4_N8 ; 30 ; Sync. load ; no ; -- ; -- ;; serializer:inst2|new_state[3]~0 ; LC_X7_Y5_N6 ; 4 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|rbyte[1]~4 ; LC_X8_Y4_N3 ; 4 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|rbyte[6]~11 ; LC_X7_Y7_N4 ; 2 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|rtms~0 ; LC_X5_Y5_N0 ; 8 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|shift[7]~0 ; LC_X6_Y4_N6 ; 8 ; Clock enable ; no ; -- ; -- ;; serializer:inst2|ssm[0] ; LC_X5_Y7_N5 ; 30 ; Sync. load ; no ; -- ; -- ;; tap_sm:inst|Equal0~2 ; LC_X4_Y4_N2 ; 7 ; Clock enable ; no ; -- ; -- ;+---------------------------------+-------------+---------+---------------------------+--------+----------------------+------------------++----------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+----------------------+-------------+---------+----------------------+------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;+----------------------+-------------+---------+----------------------+------------------+; clk ; PIN_12 ; 14 ; Global Clock ; GCLK0 ;; clock_mux:inst1|wcks ; LC_X8_Y5_N5 ; 75 ; Global Clock ; GCLK3 ;+----------------------+-------------+---------+----------------------+------------------++-------------------------------------------+; Non-Global High Fan-Out Signals ;+---------------------------------+---------+; Name ; Fan-Out ;+---------------------------------+---------+; serializer:inst2|ssm[3] ; 34 ;; serializer:inst2|ssm[1] ; 33 ;; serializer:inst2|instr ; 30 ;; serializer:inst2|ssm[0] ; 30 ;; serializer:inst2|ssm[2] ; 20 ;; serializer:inst2|dir ; 19 ;; serializer:inst2|rbyte[2] ; 19 ;; serializer:inst2|rbyte[0] ; 19 ;; serializer:inst2|rbyte[1] ; 19 ;; tap_sm:inst|state[1] ; 19 ;; serializer:inst2|db[7]~8 ; 16 ;; tap_sm:inst|state[2] ; 16 ;; tap_sm:inst|wrk ; 15 ;; serializer:inst2|sclk ; 15 ;; clock_mux:inst1|Equal0~1 ; 14 ;; tap_sm:inst|state[3] ; 14 ;; tap_sm:inst|rclk ; 14 ;; tap_sm:inst|astate[1] ; 12 ;; tap_sm:inst|state[0] ; 12 ;; serializer:inst2|rbyte[3] ; 11 ;; tap_sm:inst|astate[2] ; 10 ;; tap_sm:inst|astate[3] ; 10 ;; serializer:inst2|rbyte[7] ; 9 ;; serializer:inst2|LessThan0~0 ; 9 ;; serializer:inst2|shift[7]~0 ; 8 ;; serializer:inst2|Mux71~0 ; 8 ;; serializer:inst2|state[0] ; 8 ;; serializer:inst2|rtms~0 ; 8 ;; tap_sm:inst|astate[0] ; 8 ;; serializer:inst2|rbyte[4] ; 7 ;; serializer:inst2|rbyte[5] ; 7 ;; serializer:inst2|rbyte[6] ; 7 ;; serializer:inst2|count[3] ; 7 ;; tap_sm:inst|Equal0~2 ; 7 ;; serializer:inst2|cks[1] ; 6 ;; serializer:inst2|Mux27~0 ; 6 ;; serializer:inst2|count[0] ; 6 ;; serializer:inst2|Mux51~0 ; 5 ;; serializer:inst2|rbyte[0]~0 ; 5 ;; serializer:inst2|tms~3 ; 5 ;; tap_sm:inst|Equal3~0 ; 5 ;; tap_sm:inst|tms ; 5 ;; serializer:inst2|Add0~16 ; 4 ;; serializer:inst2|rbyte[1]~4 ; 4 ;; tap_sm:inst|Equal3~1 ; 4 ;; serializer:inst2|new_state[3]~0 ; 4 ;; serializer:inst2|cks[0] ; 4 ;; txe ; 3 ;; serializer:inst2|shift[1] ; 3 ;; serializer:inst2|shift[2] ; 3 ;+---------------------------------+---------++---------------------------------------------------+; Interconnect Usage Summary ;+----------------------------+----------------------+; Interconnect Resource Type ; Usage ;+----------------------------+----------------------+; C4s ; 220 / 1,624 ( 14 % ) ;; Direct links ; 44 / 1,930 ( 2 % ) ;; Global clocks ; 2 / 4 ( 50 % ) ;; LAB clocks ; 13 / 56 ( 23 % ) ;; LUT chains ; 16 / 513 ( 3 % ) ;; Local interconnects ; 427 / 1,930 ( 22 % ) ;; R4s ; 288 / 1,472 ( 20 % ) ;+----------------------------+----------------------++---------------------------------------------------------------------------+; LAB Logic Elements ;+--------------------------------------------+------------------------------+; Number of Logic Elements (Average = 8.75) ; Number of LABs (Total = 28) ;+--------------------------------------------+------------------------------+; 1 ; 2 ;; 2 ; 0 ;; 3 ; 1 ;; 4 ; 0 ;; 5 ; 2 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 0 ;; 9 ; 0 ;; 10 ; 23 ;+--------------------------------------------+------------------------------++-------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+------------------------------+; LAB-wide Signals (Average = 1.54) ; Number of LABs (Total = 28) ;+------------------------------------+------------------------------+; 1 Async. load ; 1 ;; 1 Clock ; 27 ;; 1 Clock enable ; 12 ;; 1 Sync. load ; 2 ;; 2 Clock enables ; 1 ;+------------------------------------+------------------------------++----------------------------------------------------------------------------+; LAB Signals Sourced ;+---------------------------------------------+------------------------------+; Number of Signals Sourced (Average = 8.96) ; Number of LABs (Total = 28) ;+---------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 2 ;; 2 ; 0 ;; 3 ; 1 ;; 4 ; 0 ;; 5 ; 2 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 0 ;; 9 ; 1 ;; 10 ; 17 ;; 11 ; 3 ;; 12 ; 2 ;+---------------------------------------------+------------------------------++--------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+------------------------------+; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 28) ;+-------------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 2 ;; 2 ; 0 ;; 3 ; 5 ;; 4 ; 3 ;; 5 ; 4 ;; 6 ; 4 ;; 7 ; 5 ;; 8 ; 2 ;; 9 ; 0 ;; 10 ; 1 ;; 11 ; 2 ;+-------------------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+------------------------------+; Number of Distinct Inputs (Average = 12.14) ; Number of LABs (Total = 28) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 0 ;; 3 ; 2 ;; 4 ; 0 ;; 5 ; 1 ;; 6 ; 0 ;; 7 ; 0 ;; 8 ; 4 ;; 9 ; 3 ;; 10 ; 0 ;; 11 ; 0 ;; 12 ; 4 ;; 13 ; 2 ;; 14 ; 3 ;; 15 ; 2 ;; 16 ; 2 ;; 17 ; 1 ;; 18 ; 2 ;; 19 ; 1 ;; 20 ; 1 ;+----------------------------------------------+------------------------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Passive Serial ;; Reserve all unused pins ; As output driving ground ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------------------------------+; Estimated Delay Added for Hold Timing ;+-----------------+----------------------+-------------------+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;+-----------------+----------------------+-------------------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Wed Jun 02 16:01:08 2010Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAGInfo: Selected device EPM570T100C5 for design "Open_JTAG"Info: Low junction temperature is 0 degrees CInfo: High junction temperature is 85 degrees CInfo: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeWarning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo: Device EPM240T100C5 is compatibleInfo: Device EPM240T100I5 is compatibleInfo: Device EPM240T100A5 is compatibleInfo: Device EPM570T100I5 is compatibleInfo: Device EPM570T100A5 is compatibleCritical Warning: No exact pin location assignment(s) for 29 pins of 29 total pinsInfo: Pin tms not assigned to an exact location on the deviceInfo: Pin rst not assigned to an exact location on the deviceInfo: Pin tck not assigned to an exact location on the deviceInfo: Pin wrk not assigned to an exact location on the deviceInfo: Pin wr not assigned to an exact location on the deviceInfo: Pin rd not assigned to an exact location on the deviceInfo: Pin tdi not assigned to an exact location on the deviceInfo: Pin trst not assigned to an exact location on the deviceInfo: Pin wcks not assigned to an exact location on the deviceInfo: Pin new_state[3] not assigned to an exact location on the deviceInfo: Pin new_state[2] not assigned to an exact location on the deviceInfo: Pin new_state[1] not assigned to an exact location on the deviceInfo: Pin new_state[0] not assigned to an exact location on the deviceInfo: Pin sm[3] not assigned to an exact location on the deviceInfo: Pin sm[2] not assigned to an exact location on the deviceInfo: Pin sm[1] not assigned to an exact location on the deviceInfo: Pin sm[0] not assigned to an exact location on the deviceInfo: Pin db[7] not assigned to an exact location on the deviceInfo: Pin db[6] not assigned to an exact location on the deviceInfo: Pin db[5] not assigned to an exact location on the deviceInfo: Pin db[4] not assigned to an exact location on the deviceInfo: Pin db[3] not assigned to an exact location on the deviceInfo: Pin db[2] not assigned to an exact location on the deviceInfo: Pin db[1] not assigned to an exact location on the deviceInfo: Pin db[0] not assigned to an exact location on the deviceInfo: Pin rxf not assigned to an exact location on the deviceInfo: Pin clk not assigned to an exact location on the deviceInfo: Pin txe not assigned to an exact location on the deviceInfo: Pin tdo not assigned to an exact location on the deviceInfo: Timing-driven compilation is using the Classic Timing AnalyzerInfo: Timing requirements not specified -- optimizing circuit to achieve the following default global requirementsInfo: Assuming a global fmax requirement of 1000 MHzInfo: Assuming a global tsu requirement of 2.0 nsInfo: Assuming a global tco requirement of 1.0 nsInfo: Assuming a global tpd requirement of 1.0 nsExtra Info: Performing register packing on registers with non-logic cell location assignmentsExtra Info: Completed register packing on registers with non-logic cell location assignmentsInfo: Completed User Assigned Global Signals Promotion OperationInfo: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 12Info: Destination "clock_mux:inst1|wcks" may be non-global or may not use global clockInfo: Automatically promoted some destinations of signal "clock_mux:inst1|wcks" to use Global clockInfo: Destination "wcks" may be non-global or may not use global clockInfo: Completed Auto Global Promotion OperationInfo: Starting register packingInfo: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic optionExtra Info: Moving registers into LUTs to improve timing and densityInfo: Started processing fast register assignmentsInfo: Finished processing fast register assignmentsExtra Info: Finished moving registers into LUTs: elapsed time is 00:00:00Info: Finished register packingInfo: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placementInfo: Number of I/O pins in group: 28 (unused VREF, 3.3V VCCIO, 4 input, 16 output, 8 bidirectional)Info: I/O standards used: 3.3-V LVTTL.Info: I/O bank details before I/O pin placementInfo: Statistics of I/O banksInfo: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins availableInfo: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins availableInfo: Fitter preparation operations ending: elapsed time is 00:00:01Info: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time is 00:00:00Info: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Fitter placement operations ending: elapsed time is 00:00:00Info: Estimated most critical path is register to pin delay of 6.057 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y7; Fanout = 3; REG Node = 'serializer:inst2|tms'Info: 2: + IC(0.620 ns) + CELL(0.740 ns) = 1.360 ns; Loc. = LAB_X9_Y7; Fanout = 1; COMB Node = 'inst4'Info: 3: + IC(2.375 ns) + CELL(2.322 ns) = 6.057 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'tms'Info: Total cell delay = 3.062 ns ( 50.55 % )Info: Total interconnect delay = 2.995 ns ( 49.45 % )Info: Fitter routing operations beginningInfo: Average interconnect usage is 15% of the available device resourcesInfo: Peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X13_Y8Info: Fitter routing operations ending: elapsed time is 00:00:00Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info: Optimizations that may affect the design's routability were skippedInfo: Optimizations that may affect the design's timing were skippedWarning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.Info: Quartus II Fitter was successful. 0 errors, 3 warningsInfo: Peak virtual memory: 175 megabytesInfo: Processing ended: Wed Jun 02 16:01:11 2010Info: Elapsed time: 00:00:03Info: Total CPU time (on all processors): 00:00:01