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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dma_rdwr_8b.s43] - Rev 202

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                              DMA INTERFACE                                */
/*---------------------------------------------------------------------------*/
/* Test the DMA interface:                                                   */
/*                        - Check Memory RD/WR features.                     */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev$                                                                */
/* $LastChangedBy$                                          */
/* $LastChangedDate$          */
/*===========================================================================*/

.include "pmem_defs.asm"

.global main

        /* ----------------------         SOME VARIABLES IN ROM  --------------- */
diverse_data:
        .word 0x0000            ; set to 1 in order to end test
        .word 0x0001            ; increment value

        /* ----------------------                 MAIN           --------------- */
main:
        ;; Disable watchdog
        mov   #0x5A80,   &WDTCTL
        
        ;; Initialize variables
        mov   #0x0000,   &DMEM_200
        mov   #0x0000,   r10
        mov   #0x0001,   r11
        mov   #0x1000,   r15

loop:   
        add   r11,                 r10
        add   &(PMEM_BASE+0x0002), &DMEM_200
        tst   &(PMEM_BASE+0x0000)
        jz    loop
        
        mov   #0x2000, r15


        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff

        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test        ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test        ; Interrupt  1                      <unused>
.word end_of_test        ; Interrupt  2                      <unused>
.word end_of_test        ; Interrupt  3                      <unused>
.word end_of_test        ; Interrupt  4                      <unused>
.word end_of_test        ; Interrupt  5                      <unused>
.word end_of_test        ; Interrupt  6                      <unused>
.word end_of_test        ; Interrupt  7                      <unused>
.word end_of_test        ; Interrupt  8                      <unused>
.word end_of_test        ; Interrupt  9                      <unused>
.word end_of_test        ; Interrupt 10                      Watchdog timer
.word end_of_test        ; Interrupt 11                      <unused>
.word end_of_test        ; Interrupt 12                      <unused>
.word end_of_test        ; Interrupt 13                      <unused>
.word end_of_test        ; Interrupt 14                      NMI
.word main               ; Interrupt 15 (highest priority)   RESET

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