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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_bis.s43] - Rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 TWO-OPERAND ARITHMETIC: BIS[.B] INSTRUCTION               */
/*---------------------------------------------------------------------------*/
/* Test the BIS[.B] instruction.                                             */
/*===========================================================================*/


.global main

main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */

        mov     #0x0000, r2
        mov     #0xaaaa, r4
        mov     #0x3333, r5
        bis          r4, r5        ;# Set bits r4 | r5 (0xaaaa | 0x3333=0xbbbb)

        mov     #0x0001, r2
        mov     #0x5555, r4
        mov     #0xcccc, r6
        bis          r4, r6        ;# Set bits r4 | r6 (0x5555 | 0xcccc=0xdddd)

        mov     #0x1000, r15


        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */

        mov     #0x0000, r2
        mov     #0x4444, r4
        mov     #0x1111, r5
        bis.b        r4, r5        ;# Set bits r4 | r5 (0x4444 | 0x1111=0x0055)

        mov     #0x0001, r2
        mov     #0x8888, r4
        mov     #0x2222, r6
        bis.b        r4, r6        ;# Set bits r4 | r6 (0x8888 | 0x2222=0x00aa)

        mov     #0x2000, r15


        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
        # 
        # Make sure Flags are unaffected by instruction
        #

        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
        mov     #0x0aaa, r4        ;#
        mov     #0x0666, r5        ;#
        bis          r4, r5        ;# Set bits r4 | r5 (0x0aaa | 0x0666=0x0eee)
        mov     #0x3000, r15

        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
        mov     #0x0aaa, r4        ;#
        mov     #0x0666, r5        ;#
        bis          r4, r5        ;# Set bits r4 | r5 (0x0aaa | 0x0666=0x0eee)
        mov     #0x3001, r15


        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
        # 
        # Make sure Flags are unaffected by instruction
        #

        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
        mov     #0x550a, r4        ;#
        mov     #0x6606, r5        ;#
        bis.b        r4, r5        ;# Set bits r4 | r5 (0x000a | 0x0006=0x000e)
        mov     #0x4000, r15

        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
        mov     #0x330a, r4        ;#
        mov     #0x9906, r5        ;#
        bis.b        r4, r5        ;# Set bits r4 | r5 (0x000a | 0x0006=0x000e)
        mov     #0x4001, r15



        /* ----------------------         END OF TEST        --------------- */
        mov      #0x5000, r15
end_of_test:
        nop
        br #0xffff


        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test  ; Interrupt  1                      <unused>
.word end_of_test  ; Interrupt  2                      <unused>
.word end_of_test  ; Interrupt  3                      <unused>
.word end_of_test  ; Interrupt  4                      <unused>
.word end_of_test  ; Interrupt  5                      <unused>
.word end_of_test  ; Interrupt  6                      <unused>
.word end_of_test  ; Interrupt  7                      <unused>
.word end_of_test  ; Interrupt  8                      <unused>
.word end_of_test  ; Interrupt  9                      <unused>
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      <unused>
.word end_of_test  ; Interrupt 12                      <unused>
.word end_of_test  ; Interrupt 13                      <unused>
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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