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<h1>Introduction</h1>
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is
compatible with Texas Instruments' <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430 microcontroller
family</a></b> and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.<br>
<br>
The core comes with some peripherals (<b>16x16 Hardware Multiplier, </b>Watchdog,
GPIO, TimerA, generic templates), with a DMA interface, and most notably with a two-wire <b>Serial
Debug Interface</b> supporting the<b> <a href="http://sourceforge.net/apps/mediawiki/mspgcc/index.php?title=MSPGCC_Wiki" target="_blank">MSPGCC</a> GNU Debugger</b> (GDB) for in-system
software debugging. <br>
<br>
While being fully FPGA friendly, this design is also particularly
suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements).<br>
In a nutshell, the openMSP430 brings with it:<br>
<ul>
<li>Low area (8k-Gates), without hidden extra infrastructure overhead (memory backbone, IRQ controller and watchdog timer are already included).</li>
<li>Excellent code density.</li>
<li>Good performances.</li>
<li>Build-in power and clock managment options.</li>
<li>Multiple times <span style="font-weight: bold;">Silicon Proven</span>.</li>
</ul>
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<br>
<h1>Download</h1>
<h3>Design</h3>
The complete tar archive of the project can be downloaded <a href="http://www.opencores.org/download,openmsp430">here</a> (OpenCores account required).<br>
<br>
The following SVN command can be run from a console (or <a href="http://www.syntevo.com/smartsvn/index.html">GUI</a>):
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<code>svn export http://opencores.org/ocsvn/openmsp430/openmsp430/trunk/ openmsp430</code>
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<br>
<h3>ChangeLog</h3>
<ul>
<li>The <a href="http://opencores.org/websvn,filedetails?repname=openmsp430&path=/openmsp430/trunk/ChangeLog_core.txt">Core's ChangeLog</a> lists the CPU updates.</li>
<li>The <a href="http://opencores.org/websvn,filedetails?repname=openmsp430&path=/openmsp430/trunk/ChangeLog_tools.txt">Tools' ChangeLog</a> lists the Software development tools updates.</li>
<li>Subscribe to the following <a href="http://opencores.org/websvn,rss?repname=openmsp430&path=/openmsp430/&isdir=1">RSS</a> feed to keep yourself informed about ALL updates.
</li></ul>
<br>
<h3>Documentation</h3>Being fully compatible with the original MSP430 architecture, TI's official documentation is applicable: <a href="http://www.ti.com/lit/ug/slau049f/slau049f.pdf">SLAU049F.PDF</a><br><br>
In addition, the openMSP430 online documentation is also available in <a href="http://opencores.org/websvn,filedetails?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2FopenMSP430.pdf" title="openMSP430 PDF Doc. R1.9">pdf</a>.<br>
<br>
<h1>Features & Limitations</h1>
<h2>Features</h2>
<ul>
<li><b>Core:</b>
<ul>
<li>Full instruction set support.</li>
<li>Interrupts: IRQs (x14, x30 or x62), NMI (x1).</li>
<li>Low Power Modes (LPMx).</li>
<li>Configurable memory size for both program and data.</li>
<li>Scalable peripheral address space.</li>
<li>DMA interface.</li>
<li>Two-wire Serial Debug Interface (I<sup>2</sup>C or UART based) with GDB support (Nexus class 3, w/o trace).</li>
<li>FPGA friendly (option for single clock domain, no clock gate).</li>
<li>ASIC friendly (options for full power & clock management support).<br>
</li>
<li>Small size (Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gates).</li>
</ul>
</li>
<br>
<li><b>Peripherals:</b>
<ul>
<li>16x16 Hardware Multiplier.</li>
<li>Basic Clock Module.</li>
<li>Watchdog.</li>
<li>Timer A (FPGA only).</li>
<li>GPIOs (FPGA only).</li>
<li>Templates for 8 and 16 bit peripherals.</li>
</ul>
</li>
</ul>
<h2>Limitations</h2>
<ul>
<li><b>Core:</b>
<ul>
<li>Instructions can't be executed from the data memory.</li>
</ul>
</li>
</ul>
<br><br>
<h1>Links</h1>
Follow on Google+:
<ul>
<li><a href="https://plus.google.com/109638736286636311338"><img style="border: 0px solid ; width: 39px; height: 39px;" alt="g+" src="https://lh6.googleusercontent.com/-0wq_FOg_8y8/Tu9AkzyXeOI/AAAAAAAAa1Y/QdtmEyJCPrA/google-plus-pages-logo.png"></a></li>
</ul>
Discussion group:
<ul>
<li><input name="hl" value="en" type="hidden">
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<img src="http://groups.google.com/intl/en/images/logos/groups_logo_sm.gif" alt="Google Groups" height="30" width="140">
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<b>Subscribe to openMSP430</b>
</td></tr>
<form action="http://groups.google.com/group/discuss_openmsp430/boxsubscribe"></form>
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Email: <input name="email" type="text">
<input name="sub" value="Subscribe" type="submit">
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<a href="http://groups.google.com/group/discuss_openmsp430?hl=en">Visit this group</a>
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</li>
</ul>
Development has been performed using the following freely available (excellent) tools:
<ul>
<li><a href="http://iverilog.icarus.com/">Icarus Verilog</a> : Verilog simulator.</li>
<li><a href="http://gtkwave.sourceforge.net/">GTKWave Analyzer</a> : Waveform viewer.</li>
<li><a href="http://sourceforge.net/apps/mediawiki/mspgcc/index.php?title=MSPGCC_Wiki">MSPGCC</a> : GCC toolchain for the Texas Instruments MSP430 MCUs.</li>
<li><a href="http://www.xilinx.com/ise/logic_design_prod/webpack.htm">ISE WebPACK</a> : Xilinx's free FPGA synthesis tool.</li>
</ul>
A few MSP430 links:
<ul>
<li><a href="http://en.wikipedia.org/wiki/MSP430">Wikipedia: MSP430</a></li>
<li><a href="http://www.ti.com/litv/pdf/slau049f">TI: MSP430x1xx Family User's Guide</a></li>
<li><a href="http://www.ti.com/lit/an/slaa205c/slaa205c.pdf">TI: MSP430 Competitive Benchmarking</a><br>
</li>
<li><a href="http://processors.wiki.ti.com/index.php/Open_Source_Projects_-_MSP430">TI: a list of available MSP430 Open Source projects out there on the web today.</a></li>
</ul>
<br><br>
<h1>Legal information</h1>MSP430 is a trademark of Texas Instruments,
Inc. This project is not affiliated in any way with Texas Instruments.
All other product names are trademarks or registered trademarks of
their respective owners. </body></html> Go to most recent revision | Compare with Previous | Blame | View Log