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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [mega/] [ram_16x8k.qip] - Rev 221
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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"set_global_assignment -name IP_TOOL_VERSION "15.0"set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_16x8k.v"]