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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [syn/] [xst/] [coregen/] [coregen.cgp] - Rev 634

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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx45
SET package = csg324
SET speedgrade = -2
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True

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