Subversion Repositories openrisc

# Paths to RTL and testbench directories for board ports.

COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl

BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl

# Only 1 include path for board builds - their own!
BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include

BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
BOARD_BENCH_VERILOG_INCLUDE_DIR=$(BOARD_BENCH_VERILOG_DIR)/include

COMMON_BENCH_DIR=$(PROJECT_ROOT)
COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
COMMON_BENCH_VERILOG_INCLUDE_DIR=$(COMMON_BENCH_VERILOG_DIR)/include

# Simulation directories
SIM_DIR ?=$(BOARD_ROOT)/sim
RTL_SIM_DIR=$(SIM_DIR)
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out

# Testbench paths
BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
COMMON_BENCH_DIR=$(PROJECT_ROOT)/bench
COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog

#COMMON_BENCH_VHDL_DIR=$(COMMON_BENCH_DIR)/vhdl
#BOARD_BENCH_VHDL_DIR=$(BOARD_BENCH_DIR)/vhdl

COMMON_BENCH_SYSC_DIR=$(COMMON_BENCH_DIR)/sysc
COMMON_BENCH_SYSC_SRC_DIR=$(COMMON_BENCH_SYSC_DIR)/src
COMMON_BENCH_SYSC_INCLUDE_DIR=$(COMMON_BENCH_SYSC_DIR)/include


# Software directories
COMMON_SW_DIR=$(PROJECT_ROOT)/sw
BOARD_SW_DIR=$(BOARD_ROOT)/sw

# Synthesis directory for board
BOARD_SYN_DIR=$(BOARD_ROOT)/syn/$(SYNTHESIS_TOOL)
BOARD_SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out