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<hr><h1>ALU<br>
<small>
[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
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<dl compact><dt><b>
ALU connectivity:</b><dd>
<br>
 <div align="center">
<img src="pavr_hwres_alu_01.gif" alt="pavr_hwres_alu_01.gif">
</div>
<br>
 <a class="el" href="group__pavr__pipeline__alu.html#alu_pipe_ref_01">Here</a> it can be seen how the ALU plugs into the pipeline. <br>
 <br>
 The ALU is a 100% <b>combinational</b> device. <br>
 It accepts 2 operands: <ul>
<li> a 16 bit operand <br>
 This is taken through the Bypass Unit. <li> an 8 bit operand <br>
 This is taken through the Bypass Unit. </ul>
The ALU output is 16 bits wide. <br>
</dl><dl compact><dt><b>
ALU opcodes:</b><dd>
<ul>
<li>NOP <br>
<li>OP1 <br>
 Transfers operand 1 directly to the ALU output. <br>
 OP2 <br>
 Transfers operand 2 directly to the lower 8 bits of ALU output. <br>
<li>ADD8 <br>
 ADC8 <br>
 Adds with carry lower 8 bits of operand 1 with operand 2. <br>
 SUB8 <br>
 SBC8 <br>
<li>AND8 <br>
 EOR8 <br>
 OR8 <br>
<li>INC8 <br>
 DEC8 <br>
<li>COM8 <br>
 NEG8 <br>
 SWAP8 <br>
<li>LSR8 <br>
 ASR8 <br>
 ROR8 <br>
<li>ADD16 <br>
 Adds without carry operand 1 with operand 2 sign extended to 16 bits. <br>
 SUB16 <br>
<li>MUL8 <br>
 MULS8 <br>
 MULSU8 <br>
 FMUL8 <br>
 FMULS8 <br>
 FMULSU8 <br>
</ul>
</dl><dl compact><dt><b>
ALU flags:</b><dd>
<ul>
<li>H (half carry)<li>S (sign)<li>V (two's complement)<li>N (negative)<li>Z (zero)<li>C (carry) </ul>
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