URL
https://opencores.org/ocsvn/pavr/pavr/trunk
Subversion Repositories pavr
[/] [pavr/] [trunk/] [doc/] [html/] [group__pavr__hwres__bpu.html] - Rev 6
Compare with Previous | Blame | View Log
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"> <title>Bypass Unit</title> <link href="doxygen.css" rel="stylesheet" type="text/css"> </head><body> <!-- Generated by Doxygen 1.2.16 --> <center> <a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="pages.html">Related Pages</a> </center> <hr><h1>Bypass Unit<br> <small> [<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small> </h1><table border=0 cellpadding=0 cellspacing=0> <tr><td colspan=2><br><h2>Modules</h2></td></tr> <tr><td nowrap align=right valign=top><a class="el" href="group__pavr__hwres__bpr0.html">Bypass chain 0</a></td></tr> <tr><td nowrap align=right valign=top><a class="el" href="group__pavr__hwres__bpr1.html">Bypass chain 1</a></td></tr> <tr><td nowrap align=right valign=top><a class="el" href="group__pavr__hwres__bpr2.html">Bypass chain 2</a></td></tr> </table> <hr><a name="_details"></a><h2>Detailed Description</h2> <dl compact><dt><b> General considerations</b><dd> The Bypass Unit (BPU) is a FIFO-like temporary storage area, that keeps data to be written into the Register File. <br> If an instruction computes a value that must be written into the Register File (RF) (an ALU instruction, for example) it first writes the BPU, and then (or at the same time) actually writes the RF. <br> If the following instructions need an operand from the RF, at the same address where the previous result should have been written into the RF, they will actually read that operand from the BPU rather than from RF. <br> This way, `read before write' pipeline hazards are avoided. <br> <br> The specific situations where BPU is needed are:<ul> <li>when reading Register File operand(s). <br> Reading Register File operands is done through the BPU.<li>when reading pointer registers. <br> Reading pointer registers is done through the BPU.</ul> </dl><dl compact><dt><b> Details</b><dd> The algorithm of using BPU: <ul> <li> the instruction that wants to write a result into the RF, writes first the BPU with 3 data fields: <ul> <li> the result itself <li> result's address into RF <li> a flag that marks this BPU entry as having valid data (a so-called `active' flag) </ul> <li> next instruction(s) that need an operand from RF, read it through a dedicated function (combinational logic), that does the following: <ul> <li> checks all BPU entries and see which ones are active (hold meaningful data). <li> compares operand's address against the addresses in all active BPU entries. <li> if a single address matches, gets the data in that BPU entry rather than data from the RF. <li> if multiple addresses match, gets the data in the most recent BPU entry. Even though it's possible that 2 matches happen at simultaneous BPU entries, this situation should never occur; it would indicate a design bug. This illegal situation would assert an error during simulation. <li> if no address matches, gets data from the RF (as if BPU were not existing). </ul> </ul> <br> The maximum delay between a write and a read from the RF is 4 clocks. Thus, the BPU FIFO-like structure has a depth of 4. <br> On the other hand, the BPU must be able to be written 3 one byte operands, at a time (must have 3 write ports). The most BPU demanding instructions are stores with pre(post) decrement(increment). Both the one byte data and a 2 byte pointer register must be written into the BPU, as well as into the RF. The 3 bytes are simultaneousely written into so-called `BPU chains' or `BPU registers' (BPU chains 0, 1, 2; or BPU registers 0, 1, 2; or BPR0, BPR1, BPR2). <br> <br> The BPU has 3x4 entries, each consisting of:<ul> <li>an 8 bit data field<li>a 5 bit address field<li>a flag that marks the entry as active or inactive</ul> </dl><dl compact><dt><b> Accessing BPU:</b><dd> <br> <div align="center"> <img src="pavr_hwres_bpu_01.gif" alt="pavr_hwres_bpu_01.gif"> </div> <br> <br> </dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by <a href="http://www.doxygen.org/index.html"> <img src="doxygen.png" alt="doxygen" align="middle" border=0 width=110 height=53></a>1.2.16 </small></address> </body> </html>